[{"id":1758817,"web_url":"http://patchwork.ozlabs.org/comment/1758817/","msgid":"<03c05a60-d697-500b-c2fc-d99b24f3f64c@twiddle.net>","list_archive_url":null,"date":"2017-08-28T17:57:25","subject":"Re: [Qemu-devel] [RFC PATCH 3/3] mttcg: Implement implicit ordering\n\tsemantics","submitter":{"id":2222,"url":"http://patchwork.ozlabs.org/api/people/2222/","name":"Richard Henderson","email":"rth@twiddle.net"},"content":"On 08/27/2017 08:53 PM, Pranith Kumar wrote:\n> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h\n> index 55a46ac825..b41a248bee 100644\n> --- a/tcg/aarch64/tcg-target.h\n> +++ b/tcg/aarch64/tcg-target.h\n> @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\n> __builtin___clear_cache((char *)start, (char *)stop);\n> }\n> \n> +#define TCG_TARGET_DEFAULT_MO (0)\n> +\n> #endif /* AARCH64_TCG_TARGET_H */\n\nPlease add all of these in one patch, separate from the tcg-op.c changes.\nWe should also just make this mandatory and remove any related #ifdefs.\n\n> +void tcg_gen_req_mo(TCGBar type)\n\nstatic, until we find that we need it somewhere else.\n\n> +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO)\n> + TCGBar order_mismatch = type & (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO);\n> + if (order_mismatch) {\n> + tcg_gen_mb(order_mismatch | TCG_BAR_SC);\n> + }\n> +#else\n> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);\n> +#endif\n\nHmm. How about\n\nstatic void tcg_gen_reg_mo(TCGBar type)\n{\n#ifdef TCG_GUEST_DEFAULT_MO\n type &= TCG_GUEST_DEFAULT_MO;\n#endif\n#ifdef TCG_TARGET_DEFAULT_MO\n type &= ~TCG_TARGET_DEFAULT_MO;\n#endif\n if (type) {\n tcg_gen_mb(type | TCG_BAR_SC);\n }\n}\n\nJust because one of those is undefined doesn't mean we can't infer tighter\nbarriers from the others, including the initial value of TYPE.\n\n> void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n> {\n> + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST);\n> memop = tcg_canonicalize_memop(memop, 0, 0);\n\nYou're putting the barrier before the load, so that should be\n\n TCG_MO_LD_LD | TCG_MO_ST_LD\n\ni.e. TCG_MO__\n\nIf you were putting the barrier afterward (an equally reasonable option), you'd\nreverse that and use what you have above.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170828035327.17146-3-bobby.prani@gmail.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:4001:c06::244","X-Mailman-Approved-At":"Mon, 28 Aug 2017 16:00:48 -0400","Subject":"Re: [Qemu-devel] [RFC PATCH 3/3] mttcg: Implement implicit ordering\n\tsemantics","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"pbonzini@redhat.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1758851,"web_url":"http://patchwork.ozlabs.org/comment/1758851/","msgid":"","list_archive_url":null,"date":"2017-08-28T21:41:29","subject":"Re: [Qemu-devel] [RFC PATCH 3/3] mttcg: Implement implicit ordering\n\tsemantics","submitter":{"id":64653,"url":"http://patchwork.ozlabs.org/api/people/64653/","name":"Pranith Kumar","email":"bobby.prani@gmail.com"},"content":"On Mon, Aug 28, 2017 at 1:57 PM, Richard Henderson wrote:\n> On 08/27/2017 08:53 PM, Pranith Kumar wrote:\n>> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h\n>> index 55a46ac825..b41a248bee 100644\n>> --- a/tcg/aarch64/tcg-target.h\n>> +++ b/tcg/aarch64/tcg-target.h\n>> @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\n>> __builtin___clear_cache((char *)start, (char *)stop);\n>> }\n>>\n>> +#define TCG_TARGET_DEFAULT_MO (0)\n>> +\n>> #endif /* AARCH64_TCG_TARGET_H */\n>\n> Please add all of these in one patch, separate from the tcg-op.c changes.\n> We should also just make this mandatory and remove any related #ifdefs.\n\nI tried looking up ordering semantics for architectures like ia64 and\ns390. It is not really clear. I think every arch but for x86 can be\ndefined as weak, even though archs like sparc can also be configured\nas TSO. Is this right?\n\n>\n>> +void tcg_gen_req_mo(TCGBar type)\n>\n> static, until we find that we need it somewhere else.\n>\n\nWill fix.\n\n>> +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO)\n>> + TCGBar order_mismatch = type & (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO);\n>> + if (order_mismatch) {\n>> + tcg_gen_mb(order_mismatch | TCG_BAR_SC);\n>> + }\n>> +#else\n>> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);\n>> +#endif\n>\n> Hmm. How about\n>\n> static void tcg_gen_reg_mo(TCGBar type)\n> {\n> #ifdef TCG_GUEST_DEFAULT_MO\n> type &= TCG_GUEST_DEFAULT_MO;\n> #endif\n> #ifdef TCG_TARGET_DEFAULT_MO\n> type &= ~TCG_TARGET_DEFAULT_MO;\n> #endif\n> if (type) {\n> tcg_gen_mb(type | TCG_BAR_SC);\n> }\n> }\n\nYes, this looks better and until we can get all the possible\ndefinitions of TCG_GUEST_DEFAULT_MO and TCG_TARGET_DEFAULT_MO figured\nout I would like to keep the #ifdefs.\n\n>\n> Just because one of those is undefined doesn't mean we can't infer tighter\n> barriers from the others, including the initial value of TYPE.\n>\n>> void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n>> {\n>> + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST);\n>> memop = tcg_canonicalize_memop(memop, 0, 0);\n>\n> You're putting the barrier before the load, so that should be\n>\n> TCG_MO_LD_LD | TCG_MO_ST_LD\n>\n> i.e. TCG_MO__\n>\n> If you were putting the barrier afterward (an equally reasonable option), you'd\n> reverse that and use what you have above.\n\nOK, will fix this. Thanks for the review.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"OkA07d68\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xh4yN53gLz9sPk\n\tfor ;\n\tTue, 29 Aug 2017 07:43:13 +1000 (AEST)","from localhost ([::1]:41531 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dmRns-00070K-Jp\n\tfor incoming@patchwork.ozlabs.org; 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charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:4001:c06::243","Subject":"Re: [Qemu-devel] [RFC PATCH 3/3] mttcg: Implement implicit ordering\n\tsemantics","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?Alex_Benn=C3=A9e?= ,\n\t\"open list:All patches CC here\" , \n\t\"open list:AArch64 target\" , \n\tPaolo Bonzini ,\n\tAurelien Jarno ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1758906,"web_url":"http://patchwork.ozlabs.org/comment/1758906/","msgid":"<45959c2a-94c3-7899-eaba-bf13ca85d052@twiddle.net>","list_archive_url":null,"date":"2017-08-28T22:39:31","subject":"Re: [Qemu-devel] [RFC PATCH 3/3] mttcg: Implement implicit ordering\n\tsemantics","submitter":{"id":2222,"url":"http://patchwork.ozlabs.org/api/people/2222/","name":"Richard Henderson","email":"rth@twiddle.net"},"content":"On 08/28/2017 02:41 PM, Pranith Kumar wrote:\n> On Mon, Aug 28, 2017 at 1:57 PM, Richard Henderson wrote:\n>> On 08/27/2017 08:53 PM, Pranith Kumar wrote:\n>>> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h\n>>> index 55a46ac825..b41a248bee 100644\n>>> --- a/tcg/aarch64/tcg-target.h\n>>> +++ b/tcg/aarch64/tcg-target.h\n>>> @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\n>>> __builtin___clear_cache((char *)start, (char *)stop);\n>>> }\n>>>\n>>> +#define TCG_TARGET_DEFAULT_MO (0)\n>>> +\n>>> #endif /* AARCH64_TCG_TARGET_H */\n>>\n>> Please add all of these in one patch, separate from the tcg-op.c changes.\n>> We should also just make this mandatory and remove any related #ifdefs.\n> \n> I tried looking up ordering semantics for architectures like ia64 and\n> s390. It is not really clear. I think every arch but for x86 can be\n> defined as weak, even though archs like sparc can also be configured\n> as TSO. Is this right?\n\ns390 has the same memory ordering as i386.\n\nBut you're right that the risc chips should generally be 0.\n\nI'll try and figure out when sparc can use PSO (loosest for sparc < 8, and\nmodern niagara), but leave it 0 for now.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"fMrtAJl3\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xh6Ct0KNzz9s83\n\tfor ;\n\tTue, 29 Aug 2017 08:40:08 +1000 (AEST)","from localhost ([::1]:41682 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dmShS-0002LB-6M\n\tfor incoming@patchwork.ozlabs.org; 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