[{"id":1758385,"web_url":"http://patchwork.ozlabs.org/comment/1758385/","msgid":"<3c53e6a3-4628-9496-345f-65666af4efc1@ti.com>","list_archive_url":null,"date":"2017-08-28T06:19:44","subject":"Re: [U-Boot] [PATCH] ARM: DRA72x: Add support for detection of\n\tDRA71x SR 2.1","submitter":{"id":14145,"url":"http://patchwork.ozlabs.org/api/people/14145/","name":"Lokesh Vutla","email":"lokeshvutla@ti.com"},"content":"+ Tom\n\nOn 8/27/2017 3:21 AM, Vishal Mahaveer wrote:\n> DRA71x processors are reduced pin and software compatible\n> derivative of DRA72 processors. Add support for detection\n> of SR2.1 version of DRA71x family of processors.\n> \n> Signed-off-by: Vishal Mahaveer \n\nReviewed-by: Lokesh Vutla \n\nThanks and regards,\nLokesh\n\n> ---\n> arch/arm/include/asm/arch-omap5/omap.h | 1 +\n> arch/arm/include/asm/omap_common.h | 1 +\n> arch/arm/mach-omap2/omap5/hw_data.c | 2 ++\n> arch/arm/mach-omap2/omap5/hwinit.c | 3 +++\n> arch/arm/mach-omap2/omap5/sdram.c | 2 ++\n> board/ti/dra7xx/evm.c | 3 +++\n> 6 files changed, 12 insertions(+)\n> \n> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h\n> index b047f0d..6705544 100644\n> --- a/arch/arm/include/asm/arch-omap5/omap.h\n> +++ b/arch/arm/include/asm/arch-omap5/omap.h\n> @@ -63,6 +63,7 @@\n> #define DRA752_CONTROL_ID_CODE_ES2_0\t\t0x2B99002F\n> #define DRA722_CONTROL_ID_CODE_ES1_0\t\t0x0B9BC02F\n> #define DRA722_CONTROL_ID_CODE_ES2_0\t\t0x1B9BC02F\n> +#define DRA722_CONTROL_ID_CODE_ES2_1\t\t0x2B9BC02F\n> \n> /* UART */\n> #define UART1_BASE\t\t(OMAP54XX_L4_PER_BASE + 0x6a000)\n> diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h\n> index ef5c481..46ee9c2 100644\n> --- a/arch/arm/include/asm/omap_common.h\n> +++ b/arch/arm/include/asm/omap_common.h\n> @@ -766,6 +766,7 @@ static inline u8 is_dra72x(void)\n> #define DRA752_ES2_0\t0x07520200\n> #define DRA722_ES1_0\t0x07220100\n> #define DRA722_ES2_0\t0x07220200\n> +#define DRA722_ES2_1\t0x07220210\n> \n> /*\n> * silicon device type\n> diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c\n> index 4ad6b53..06a9fd2 100644\n> --- a/arch/arm/mach-omap2/omap5/hw_data.c\n> +++ b/arch/arm/mach-omap2/omap5/hw_data.c\n> @@ -719,6 +719,7 @@ void __weak hw_data_init(void)\n> \n> \tcase DRA722_ES1_0:\n> \tcase DRA722_ES2_0:\n> +\tcase DRA722_ES2_1:\n> \t*prcm = &dra7xx_prcm;\n> \t*dplls_data = &dra72x_dplls;\n> \t*ctrl = &dra7xx_ctrl;\n> @@ -753,6 +754,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)\n> \t\t*regs = &ioregs_dra72x_es1;\n> \t\tbreak;\n> \tcase DRA722_ES2_0:\n> +\tcase DRA722_ES2_1:\n> \t\t*regs = &ioregs_dra72x_es2;\n> \t\tbreak;\n> \n> diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c\n> index afe59e0..d53900f 100644\n> --- a/arch/arm/mach-omap2/omap5/hwinit.c\n> +++ b/arch/arm/mach-omap2/omap5/hwinit.c\n> @@ -377,6 +377,9 @@ void init_omap_revision(void)\n> \tcase DRA722_CONTROL_ID_CODE_ES2_0:\n> \t\t*omap_si_rev = DRA722_ES2_0;\n> \t\tbreak;\n> +\tcase DRA722_CONTROL_ID_CODE_ES2_1:\n> +\t\t*omap_si_rev = DRA722_ES2_1;\n> +\t\tbreak;\n> \tdefault:\n> \t\t*omap_si_rev = OMAP5430_SILICON_ID_INVALID;\n> \t}\n> diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c\n> index 7712923..684b5bc 100644\n> --- a/arch/arm/mach-omap2/omap5/sdram.c\n> +++ b/arch/arm/mach-omap2/omap5/sdram.c\n> @@ -481,6 +481,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,\n> \t\t*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);\n> \t\tbreak;\n> \tcase DRA722_ES2_0:\n> +\tcase DRA722_ES2_1:\n> \t\t*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;\n> \t\t*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);\n> \t\tbreak;\n> @@ -714,6 +715,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)\n> \tcase DRA752_ES2_0:\n> \tcase DRA722_ES1_0:\n> \tcase DRA722_ES2_0:\n> +\tcase DRA722_ES2_1:\n> \t\tbug_00339_regs_ptr = dra_bug_00339_regs;\n> \t\t*iterations = sizeof(dra_bug_00339_regs)/\n> \t\t\t sizeof(dra_bug_00339_regs[0]);\n> diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c\n> index 93d3d0b..58feb15 100644\n> --- a/board/ti/dra7xx/evm.c\n> +++ b/board/ti/dra7xx/evm.c\n> @@ -236,6 +236,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)\n> \t\tbreak;\n> \tcase DRA722_ES1_0:\n> \tcase DRA722_ES2_0:\n> +\tcase DRA722_ES2_1:\n> \t\tif (ram_size < CONFIG_MAX_MEM_MAPPED)\n> \t\t\t*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;\n> \t\telse\n> @@ -299,6 +300,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)\n> \t\tbreak;\n> \tcase DRA722_ES1_0:\n> \tcase DRA722_ES2_0:\n> +\tcase DRA722_ES2_1:\n> \tdefault:\n> \t\tif (ram_size < CONFIG_MAX_MEM_MAPPED)\n> \t\t\t*dmm_lisa_regs = &lisa_map_2G_x_2;\n> @@ -643,6 +645,7 @@ void recalibrate_iodelay(void)\n> \tswitch (omap_revision()) {\n> \tcase DRA722_ES1_0:\n> \tcase DRA722_ES2_0:\n> +\tcase DRA722_ES2_1:\n> \t\tpads = dra72x_core_padconf_array_common;\n> \t\tnpads = ARRAY_SIZE(dra72x_core_padconf_array_common);\n> \t\tif (board_is_dra71x_evm()) {\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1503901188;\n\tbh=DPUN4dYjcQj6eLTZOvlE05qQ/swmCNIWFtcdKz67gek=;\n\th=Subject:To:References:From:Date:In-Reply-To;\n\tb=ecFS2VkH2Fmh2sbmxGGMHACK7/15n0H23UpYa4Wgc5JoAKG6unQf9+ELwtT6eOak3\n\t2XM5pKE19vU353QV7cF73jO4LG8OLirty0cDB55+6g0Pi/jb/+Zfw83i2EAqfmKAQp\n\thoPt82aen25k/PXMFRMmy3Vo0pFy0sKHav4q9oec=","To":"Vishal Mahaveer , , Tom Rini\n\t","References":"<1503784282-13461-1-git-send-email-vishalm@ti.com>","From":"Lokesh Vutla ","Message-ID":"<3c53e6a3-4628-9496-345f-65666af4efc1@ti.com>","Date":"Mon, 28 Aug 2017 11:49:44 +0530","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1503784282-13461-1-git-send-email-vishalm@ti.com>","Content-Language":"en-GB","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Subject":"Re: [U-Boot] [PATCH] ARM: DRA72x: Add support for detection of\n\tDRA71x SR 2.1","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1767505,"web_url":"http://patchwork.ozlabs.org/comment/1767505/","msgid":"<20170913023004.GW4474@bill-the-cat>","list_archive_url":null,"date":"2017-09-13T02:30:04","subject":"Re: [U-Boot] ARM: DRA72x: Add support for detection of DRA71x SR 2.1","submitter":{"id":65875,"url":"http://patchwork.ozlabs.org/api/people/65875/","name":"Tom Rini","email":"trini@konsulko.com"},"content":"On Sat, Aug 26, 2017 at 04:51:22PM -0500, Vishal Mahaveer wrote:\n\n> DRA71x processors are reduced pin and software compatible\n> derivative of DRA72 processors. Add support for detection\n> of SR2.1 version of DRA71x family of processors.\n> \n> Signed-off-by: Vishal Mahaveer \n> Reviewed-by: Lokesh Vutla \n\nApplied to u-boot/master, thanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=konsulko.com header.i=@konsulko.com\n\theader.b=\"ZLjx3ygb\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsR9D60Nqz9t30\n\tfor ;\n\tWed, 13 Sep 2017 12:55:12 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 9F601C2246B; Wed, 13 Sep 2017 02:35:10 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 0E292C22394;\n\tWed, 13 Sep 2017 02:35:00 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid B429EC2236C; Wed, 13 Sep 2017 02:30:11 +0000 (UTC)","from mail-yw0-f175.google.com (mail-yw0-f175.google.com\n\t[209.85.161.175])\n\tby lists.denx.de (Postfix) with ESMTPS id E98CCC22370\n\tfor ; Wed, 13 Sep 2017 02:30:07 +0000 (UTC)","by mail-yw0-f175.google.com with SMTP id q80so32076447ywg.2\n\tfor ; Tue, 12 Sep 2017 19:30:07 -0700 (PDT)","from bill-the-cat ([2606:a000:140b:dc:202f:e2cf:a300:56c])\n\tby smtp.gmail.com with ESMTPSA id\n\tx21sm3014886ywg.34.2017.09.12.19.30.05\n\t(version=TLS1_2 cipher=AES128-SHA bits=128/128);\n\tTue, 12 Sep 2017 19:30:05 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=konsulko.com;\n\ts=google; \n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=MXxlSiVfKmtX3Smzrbnqrr7pyvgXchQizi0yORZLvuY=;\n\tb=ZLjx3ygbmk4+P6qA1hgP/D9U+OmCshpyyQqVcUG22b4bZSRh3NAbBIENtzEVIvpNfB\n\t07sfdaaUvpHUL0oP7aKccmYpQBNFEtbB66/ZgQhRut5fncCtTEOHm6KvlCvAmyfEo7c2\n\tpnGo6/Im7PNr3YLXCiDLhr4L49Xi1gsi4M7Cs=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=MXxlSiVfKmtX3Smzrbnqrr7pyvgXchQizi0yORZLvuY=;\n\tb=Vquek3j0/L9oFcXVFGY5rlaiP96FWt0IWVZCl4lP3eYUbQbQJfKIfWwVKht7XPkjBy\n\tnxD9nlYdOZqQDYfbSjx3t/a3BA7cuYafw2BHD0yC2BZz1OYl6T4efSDpEa+e8CrbrsPy\n\tqklY8Wej+bBH9/vRzYW1akQDoQx9cwDfbS7CITsCzwgZzdhR0H2Obw0PVCWyG5haGLDA\n\tmFA23Z3CBPtJCuSztygENDRSI5SpVrjV9tl8ZtfZBmUT5UGbv4TdJz/JTe+4dr6nY2cs\n\tHPg58UIXADUp3ceSVDyPpHdQOHf9B3u4zo7VzqbP57oa79Jb+CwPkWeoYU1jUBOMcFlp\n\tklvw==","X-Gm-Message-State":"AHPjjUiWCs8jwdXupGdNCLVWiWAsFsRBNahlypkuhPCQGbXXAgcX3VPn\n\t7WMbYoritYTXLmOoyXXIBQ==","X-Google-Smtp-Source":"ADKCNb6mKTy6PggljQO1QQqHQX/46deJ+AKjZY0tOUz1AQMyuD1vmJp45dlS92Exgq4Oif54Tx+0qA==","X-Received":"by 10.129.110.137 with SMTP id\n\tj131mr13955908ywc.221.1505269806877; \n\tTue, 12 Sep 2017 19:30:06 -0700 (PDT)","Date":"Tue, 12 Sep 2017 22:30:04 -0400","From":"Tom Rini ","To":"Vishal Mahaveer ","Message-ID":"<20170913023004.GW4474@bill-the-cat>","References":"<1503784282-13461-1-git-send-email-vishalm@ti.com>","MIME-Version":"1.0","In-Reply-To":"<1503784282-13461-1-git-send-email-vishalm@ti.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Cc":"u-boot@lists.denx.de","Subject":"Re: [U-Boot] ARM: DRA72x: Add support for detection of DRA71x SR 2.1","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"multipart/mixed;\n\tboundary=\"===============8186961360698273608==\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]