[{"id":1761215,"web_url":"http://patchwork.ozlabs.org/comment/1761215/","msgid":"<20170831173920.4emtr5vkgvjcx6ac@rob-hp-laptop>","list_archive_url":null,"date":"2017-08-31T17:39:20","subject":"Re: [PATCH 2/7] dt-bindings: PM / OPP: add clocks per OPP node\n\tsupport","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Aug 24, 2017 at 12:10:05AM +0800, Dong Aisheng wrote:\n> It's used for platforms where different OPPs may use different clocks.\n> With this extended binding, user could specify the correct clock for each\n> OPP node.\n> \n> Cc: Viresh Kumar \n> Cc: Nishanth Menon \n> Cc: Stephen Boyd \n> Cc: \"Rafael J. Wysocki\" \n> Cc: Rob Herring \n> Cc: Frank Rowand \n> Cc: devicetree@vger.kernel.org\n> Signed-off-by: Dong Aisheng \n> ---\n> Documentation/devicetree/bindings/opp/opp.txt | 52 +++++++++++++++++++++++++++\n> 1 file changed, 52 insertions(+)\n> \n> diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt\n> index e36d261..40a4340 100644\n> --- a/Documentation/devicetree/bindings/opp/opp.txt\n> +++ b/Documentation/devicetree/bindings/opp/opp.txt\n> @@ -152,6 +152,11 @@ Optional properties:\n> hierarchy can be contained in multiple 32 bit values. i.e. in the\n> above example, Z1 & Z2 refer to the version hierarchy Z.\n> \n> +- clocks: Clock phandle and specifier used for this opp.\n> +\n> +- clock-names: clock names for this opp. The valid clock names are platform\n> +\t specific.\n\nYou don't need -names if there's only 1 clock. But then how long until \nwe have a list of any random clocks some how associated with an OPP.\n\nI think this should really be solved within the clock framework. What \nyou really need is \"set my parent clock to the source that can provide X \nHz\". Could the assigned-clocks property work here (in the OPP nodes \nrather than the cpu nodes)?\n\n> +\n> - status: Marks the node enabled/disabled.\n> \n> Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.\n> @@ -528,3 +533,50 @@ Example 6: opp-microvolt-, opp-microamp-:\n> \t\t};\n> \t};\n> };\n> +\n> +Example 7: Single core ARM cortex A7, switch separate clocks for each OPP:\n\nCan't you add this to an existing example? We don't need to enumerate \nevery possible option.\n\nRob\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjqPh3XnGz9sPt\n\tfor ;\n\tFri, 1 Sep 2017 03:39:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751858AbdHaRjX (ORCPT\n\t);\n\tThu, 31 Aug 2017 13:39:23 -0400","from mail-oi0-f66.google.com ([209.85.218.66]:35449 \"EHLO\n\tmail-oi0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751258AbdHaRjW (ORCPT\n\t); Thu, 31 Aug 2017 13:39:22 -0400","by mail-oi0-f66.google.com with SMTP id k77so270222oib.2;\n\tThu, 31 Aug 2017 10:39:21 -0700 (PDT)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\tp128sm272425oif.33.2017.08.31.10.39.20\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 31 Aug 2017 10:39:20 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=lizhS7bISI8hbWQUm7V3wyjOH/8j52QHr/3KVXaj8KI=;\n\tb=bAsiSiwIYE9/O3JmN84XIVj113ZY74WhXEGLsQe7wYbxuYenA2fLgSOh7utb9GKokq\n\tu/Yddx1GImcs/P3KgoesJ3DGOJ6rzdqAwgImYX/PQwCD0ekIFhOYgz7saKkPyNyidvXS\n\t6rC4kWjj/CkPs6jrI7dwiTo76JHokpLG+RFfAtadqRqABC2J6ts9ku9viepmsen1XYou\n\tqOfmJkYLEqJJbqDQ7zogAb2wnAdxT42lQs1n65fWbUx4d0qNRtcr0+htpNTZfJFzk2fh\n\tPhXFTiHlkouVRju3Cpy89E061GYSMnB8pRuQUAXE6K8J3eBDJb7I7prA9qikakT+Q6fy\n\tAMRQ==","X-Gm-Message-State":"AHPjjUiGCZ3Dn9jExF8TDhN/GPyN7h8saCfZ5tnIZPIVJVQ1AZiI8ReF\n\tqRcPSmMjngZSVJJFF20=","X-Google-Smtp-Source":"ADKCNb5b+RAe5s+8VIW1bcQsP0NGJdxhJFafEfZhalKUltvGk8MfqN2OzbWGRyM00SIoqfbJyB0r1Q==","X-Received":"by 10.202.46.79 with SMTP id u76mr1153589oiu.63.1504201161348;\n\tThu, 31 Aug 2017 10:39:21 -0700 (PDT)","Date":"Thu, 31 Aug 2017 12:39:20 -0500","From":"Rob Herring ","To":"Dong Aisheng ","Cc":"linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, sboyd@codeaurora.org,\n\tvireshk@kernel.org, nm@ti.com, rjw@rjwysocki.net,\n\tshawnguo@kernel.org, Anson.Huang@nxp.com, ping.bai@nxp.com,\n\tFrank Rowand , devicetree@vger.kernel.org","Subject":"Re: [PATCH 2/7] dt-bindings: PM / OPP: add clocks per OPP node\n\tsupport","Message-ID":"<20170831173920.4emtr5vkgvjcx6ac@rob-hp-laptop>","References":"<1503504610-12880-1-git-send-email-aisheng.dong@nxp.com>\n\t<1503504610-12880-3-git-send-email-aisheng.dong@nxp.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1503504610-12880-3-git-send-email-aisheng.dong@nxp.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1761666,"web_url":"http://patchwork.ozlabs.org/comment/1761666/","msgid":"<20170901130132.GA22788@b29396-OptiPlex-7040>","list_archive_url":null,"date":"2017-09-01T13:01:32","subject":"Re: [PATCH 2/7] dt-bindings: PM / OPP: add clocks per OPP node\n\tsupport","submitter":{"id":8521,"url":"http://patchwork.ozlabs.org/api/people/8521/","name":"Dong Aisheng","email":"dongas86@gmail.com"},"content":"On Thu, Aug 31, 2017 at 12:39:20PM -0500, Rob Herring wrote:\n> On Thu, Aug 24, 2017 at 12:10:05AM +0800, Dong Aisheng wrote:\n> > It's used for platforms where different OPPs may use different clocks.\n> > With this extended binding, user could specify the correct clock for each\n> > OPP node.\n> > \n> > Cc: Viresh Kumar \n> > Cc: Nishanth Menon \n> > Cc: Stephen Boyd \n> > Cc: \"Rafael J. Wysocki\" \n> > Cc: Rob Herring \n> > Cc: Frank Rowand \n> > Cc: devicetree@vger.kernel.org\n> > Signed-off-by: Dong Aisheng \n> > ---\n> > Documentation/devicetree/bindings/opp/opp.txt | 52 +++++++++++++++++++++++++++\n> > 1 file changed, 52 insertions(+)\n> > \n> > diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt\n> > index e36d261..40a4340 100644\n> > --- a/Documentation/devicetree/bindings/opp/opp.txt\n> > +++ b/Documentation/devicetree/bindings/opp/opp.txt\n> > @@ -152,6 +152,11 @@ Optional properties:\n> > hierarchy can be contained in multiple 32 bit values. i.e. in the\n> > above example, Z1 & Z2 refer to the version hierarchy Z.\n> > \n> > +- clocks: Clock phandle and specifier used for this opp.\n> > +\n> > +- clock-names: clock names for this opp. The valid clock names are platform\n> > +\t specific.\n> \n> You don't need -names if there's only 1 clock.\n\nGot it, will remove -name.\n\n> But then how long until \n> we have a list of any random clocks some how associated with an OPP.\n> \n\nNot sure whether it will really happen in the future. Even it happens,\nas we usually only need the device parent clock, then probably better to\nhandle the left complicated things in clock driver or OPP device driver.\n\n> I think this should really be solved within the clock framework. What \n> you really need is \"set my parent clock to the source that can provide X \n> Hz\". Could the assigned-clocks property work here (in the OPP nodes \n> rather than the cpu nodes)?\n> \n\nI'm not quite sure i got your point. assigned-clocks seems a bit like function\nthe same as clocks property here, both are used to specifying the device\nparent clock which provide X hz.\n\nOr are you suggesting using assigned-clocks/assigned-clocks-rates instread\nof clocks/opp-hz? Would you please clarify a bit more?\n\n> > +\n> > - status: Marks the node enabled/disabled.\n> > \n> > Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.\n> > @@ -528,3 +533,50 @@ Example 6: opp-microvolt-, opp-microamp-:\n> > \t\t};\n> > \t};\n> > };\n> > +\n> > +Example 7: Single core ARM cortex A7, switch separate clocks for each OPP:\n> \n> Can't you add this to an existing example? We don't need to enumerate \n> every possible option.\n\nOkay, Will merge it.\n\nThanks\n\nRegards\nDong Aisheng\n\n> \n> Rob\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"PyoSQU64\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkKBp0NgPz9t2d\n\tfor ;\n\tFri, 1 Sep 2017 23:01:54 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751963AbdIANBj (ORCPT\n\t);\n\tFri, 1 Sep 2017 09:01:39 -0400","from mail-pg0-f66.google.com ([74.125.83.66]:37031 \"EHLO\n\tmail-pg0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751778AbdIANBi (ORCPT\n\t); Fri, 1 Sep 2017 09:01:38 -0400","by mail-pg0-f66.google.com with SMTP id t193so81678pgc.4;\n\tFri, 01 Sep 2017 06:01:38 -0700 (PDT)","from b29396-OptiPlex-7040 (gate-zmy3.freescale.com. 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