[{"id":1757176,"web_url":"http://patchwork.ozlabs.org/comment/1757176/","msgid":"","list_archive_url":null,"date":"2017-08-25T08:35:45","subject":"Re: [PATCH 2/2] clk: renesas: cpg-mssr: add R8A7797 support","submitter":{"id":703,"url":"http://patchwork.ozlabs.org/api/people/703/","name":"Geert Uytterhoeven","email":"geert@linux-m68k.org"},"content":"Hi Sergei,\n\nOn Wed, Aug 23, 2017 at 2:52 PM, Sergei Shtylyov\n wrote:\n> Add R-Car V3M (R8A7797) Clock Pulse Generator / Module Standby and\n> Software Reset support, using the CPG/MSSR driver core and the common\n> R-Car Gen3 code.\n>\n> Based on the original (and large) patch by Daisuke Matsushita\n> .\n>\n> Signed-off-by: Vladimir Barinov \n> Signed-off-by: Sergei Shtylyov \n\nThanks for your patch!\n\n> +++ linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n> @@ -22,6 +22,7 @@ Required Properties:\n> - \"renesas,r8a7794-cpg-mssr\" for the r8a7794 SoC (R-Car E2)\n> - \"renesas,r8a7795-cpg-mssr\" for the r8a7795 SoC (R-Car H3)\n> - \"renesas,r8a7796-cpg-mssr\" for the r8a7796 SoC (R-Car M3-W)\n> + - \"renesas,r8a7797-cpg-mssr\" for the r8a7797 SoC (R-Car V3M)\n\nPlease use \"renesas,r8a77970-cpg-mssr\", to follow the new 5-digit scheme\nstarted with r8a77995, and \"r8a77970\".\n\n> @@ -30,8 +31,8 @@ Required Properties:\n> clock-names\n> - clock-names: List of external parent clock names. Valid names are:\n> - \"extal\" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,\n> - r8a7795, r8a7796)\n> - - \"extalr\" (r8a7795, r8a7796)\n> + r8a7795, r8a7796, r8a7797)\n> + - \"extalr\" (r8a7795, r8a7796, r8a7797)\n\nLikewise.\n\n> --- linux.orig/drivers/clk/renesas/Kconfig\n> +++ linux/drivers/clk/renesas/Kconfig\n> @@ -15,6 +15,7 @@ config CLK_RENESAS\n> select CLK_R8A7794 if ARCH_R8A7794\n> select CLK_R8A7795 if ARCH_R8A7795\n> select CLK_R8A7796 if ARCH_R8A7796\n> + select CLK_R8A7797 if ARCH_R8A7797\n\nThere's no ARCH_R8A7797 yet.\nShould be CLK_R8A77970 and ARCH_R8A77970.\n\n> select CLK_SH73A0 if ARCH_SH73A0\n>\n> if CLK_RENESAS\n> @@ -94,6 +95,10 @@ config CLK_R8A7796\n> bool\n> select CLK_RCAR_GEN3_CPG\n>\n> +config CLK_R8A7797\n\nCLK_R8A77970\n\n> + bool\n\nbool \"R-Car V3M clock support\" if COMPILE_TEST\n\n> --- linux.orig/drivers/clk/renesas/Makefile\n> +++ linux/drivers/clk/renesas/Makefile\n> @@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cp\n> obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o\n> obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o\n> obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o\n> +obj-$(CONFIG_CLK_R8A7797) += r8a7797-cpg-mssr.o\n\n...77970...\n\n> obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o\n>\n> # Family\n> Index: linux/drivers/clk/renesas/r8a7797-cpg-mssr.c\n> ===================================================================\n> --- /dev/null\n> +++ linux/drivers/clk/renesas/r8a7797-cpg-mssr.c\n\n...77970...\n\n> + /* Internal Core Clocks */\n\n> + CLK_S1,\n> + CLK_S2,\n\nThere are no S1 and S2 clocks in Figure 8.1c.\n\n> +static const struct cpg_core_clk r8a7797_core_clks[] __initconst = {\n\n> + /* Internal Core Clocks */\n\n> + DEF_FIXED(\".s1\", CLK_S1, CLK_PLL1_DIV2, 4, 1),\n> + DEF_FIXED(\".s2\", CLK_S2, CLK_PLL1_DIV2, 6, 1),\n\nThere are no S1 and S2 clocks in Figure 8.1c.\n\n> + /* Core Clock Outputs */\n\n> + DEF_FIXED(\"s1d1\", R8A7797_CLK_S1D1, CLK_S1, 1, 1),\n> + DEF_FIXED(\"s1d2\", R8A7797_CLK_S1D2, CLK_S1, 2, 1),\n> + DEF_FIXED(\"s1d4\", R8A7797_CLK_S1D4, CLK_S1, 4, 1),\n> + DEF_FIXED(\"s2d1\", R8A7797_CLK_S2D1, CLK_S2, 1, 1),\n> + DEF_FIXED(\"s2d2\", R8A7797_CLK_S2D2, CLK_S2, 2, 1),\n> + DEF_FIXED(\"s2d4\", R8A7797_CLK_S2D4, CLK_S2, 4, 1),\n\nThere are no S1 and S2 clocks in Figure 8.1c.\nPlease divide CLK_PLL1_DIV2 directly.\n\n> +static const struct mssr_mod_clk r8a7797_mod_clks[] __initconst = {\n\nAs usual, I could not verify all parent clocks.\n\n> +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {\n> + /* EXTAL div PLL1 mult PLL3 mult */\n\nThis struct recently gained a \"PLL1 div\" column, which should be all ones\nfor V3M.\n\n> +static int __init r8a7797_cpg_mssr_init(struct device *dev)\n> +{\n> + const struct rcar_gen3_cpg_pll_config *cpg_pll_config;\n> + u32 cpg_mode;\n> + int error;\n> +\n> + error = rcar_rst_read_mode_pins(&cpg_mode);\n> + if (error)\n> + return error;\n> +\n> + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];\n> + if (!cpg_pll_config->extal_div) {\n\nThis check is not needed on V3M, as all 8 combinations are valid.\n\n> --- linux.orig/drivers/clk/renesas/renesas-cpg-mssr.c\n> +++ linux/drivers/clk/renesas/renesas-cpg-mssr.c\n> @@ -680,6 +680,12 @@ static const struct of_device_id cpg_mss\n> .data = &r8a7796_cpg_mssr_info,\n> },\n> #endif\n> +#ifdef CONFIG_CLK_R8A7797\n> + {\n> + .compatible = \"renesas,r8a7797-cpg-mssr\",\n> + .data = &r8a7797_cpg_mssr_info,\n> + },\n> +#endif\n\n...77970...\n\n> --- linux.orig/drivers/clk/renesas/renesas-cpg-mssr.h\n> +++ linux/drivers/clk/renesas/renesas-cpg-mssr.h\n> @@ -138,6 +138,7 @@ extern const struct cpg_mssr_info r8a779\n> extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;\n> extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;\n> extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;\n> +extern const struct cpg_mssr_info r8a7797_cpg_mssr_info;\n\n...77970...\n\nGr{oetje,eeting}s,\n\n Geert\n\n--\nGeert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org\n\nIn personal conversations with technical people, I call myself a hacker. But\nwhen I'm talking to journalists I just say \"programmer\" or something like that.\n -- Linus Torvalds\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"fk/4dNLa\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xdvd95vKsz9sRm\n\tfor ;\n\tFri, 25 Aug 2017 18:35:57 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755179AbdHYIfv (ORCPT\n\t);\n\tFri, 25 Aug 2017 04:35:51 -0400","from mail-pg0-f67.google.com ([74.125.83.67]:37317 \"EHLO\n\tmail-pg0-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1755168AbdHYIfr (ORCPT\n\t); Fri, 25 Aug 2017 04:35:47 -0400","by mail-pg0-f67.google.com with SMTP id a7so2966819pgn.4;\n\tFri, 25 Aug 2017 01:35:46 -0700 (PDT)","by 10.100.161.139 with HTTP; Fri, 25 Aug 2017 01:35:45 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:sender:in-reply-to:references:from:date:message-id\n\t:subject:to:cc;\n\tbh=9QJmkk3e11yIdHg5+GcheM+I/xx4zhfdNG1ERPKz0uU=;\n\tb=fk/4dNLaUQjpUoBn3x+FobdarvP9170kZ8exmahR0DrSkBmlIKZrB3/uuZ9j428GEB\n\tYpb98XlNN34CqvFKpWc34OSR6TGt2FKjbJ8nep+8m/VI/el9jLFC3bg9bPKbn4tslng2\n\trY2Amz36RCHjqii59BjOtL230dhXZcrVQcItPpWMaS0WvRqvsLGt4QzLlx+j4qITSFvA\n\t+nlJeV1r956FBzLzb57bFO7wA5Ag9p/OILoQZA5cagzRHHTAgvnrzg9i/yyEY05O4iUc\n\tLzS+TLfWzac3aH92K/6hXInyXbkJd2O0eCQNnzpyo1iLgaZv9WaFBNPGy9JBiKTh9glB\n\t5AIg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:sender:in-reply-to:references:from\n\t:date:message-id:subject:to:cc;\n\tbh=9QJmkk3e11yIdHg5+GcheM+I/xx4zhfdNG1ERPKz0uU=;\n\tb=rOouFSu7xwfrMXssyUD7hru8tRi7GHjQYnIVr2VPEhJ5aAX+11RpbnjHb2h5VDLMGz\n\tKBsjdiAy0f6rLM5rhM1BdDP9xQP2dur5gxXNTdmRWZddwLGCRK21/i868c5BcH06os0s\n\tRODLfzl/YKkPIcI9ESS41m0/cF+RoQWt+nt4iVzn1tuzFFWYcAdJ51G0A+YtOtwUaSSd\n\tXRvHFI7c4quZ4WOX4uy4ZnkonR7n4u4hN788tmTWO1kCv9+tH2g9N5h0JIZwNtqwJdVi\n\tzxet7sF7oK6F6JV858pZWEuIz00Tuk8qGHYDCM11W+vNf+NT+IysOglG0GwDjFTT5tNg\n\t+Cvw==","X-Gm-Message-State":"AHYfb5jEoFExkjcJw6bLmOR3Nsf+Pydh39t1h/l8DTQY2oywkLRmLyMg\n\tI2bwaBxEAsnLsFhoOcvSZWwvfssEKQ==","X-Received":"by 10.99.123.79 with SMTP id k15mr8914984pgn.433.1503650146289; \n\tFri, 25 Aug 2017 01:35:46 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170823125744.424675523@cogentembedded.com>","References":"<20170823125744.424675523@cogentembedded.com>","From":"Geert Uytterhoeven ","Date":"Fri, 25 Aug 2017 10:35:45 +0200","X-Google-Sender-Auth":"YycUVARtMY9IgDWGWBg7bMieVYk","Message-ID":"","Subject":"Re: [PATCH 2/2] clk: renesas: cpg-mssr: add R8A7797 support","To":"Sergei Shtylyov ","Cc":"Michael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tMark Rutland ,\n\tGeert Uytterhoeven ,\n\tlinux-clk ,\n\t\"devicetree@vger.kernel.org\" ,\n\tLinux-Renesas ,\n\tVladimir Barinov ,\n\tSimon Horman ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]