[{"id":1759113,"web_url":"http://patchwork.ozlabs.org/comment/1759113/","msgid":"<1503994514.5933.8.camel@aj.id.au>","list_archive_url":null,"date":"2017-08-29T08:15:14","subject":"Re: [PATCH linux dev-4.10 resend] dts: add aspeed-pwm-tacho to msn\n\tdts.","submitter":{"id":68332,"url":"http://patchwork.ozlabs.org/api/people/68332/","name":"Andrew Jeffery","email":"andrew@aj.id.au"},"content":"Hi Mykola,\n\nSorry for taking so long to review this, thanks for the prompt with the resend.\n\nUnfortunately the patch doesn't apply cleanly to dev-4.10 - can you please\nrebase it and send a v2?\n\nI have some additional queries below.\n\nOn Wed, 2017-08-23 at 10:33 +0300, Mykola Kostenok wrote:\n> Add basic pwm-tacho-controller node to ast-g5 dtsi.\n> \n> Add pwm-tacho to aspeed-bmc-mellanox-msn.dts.\n> \n> > Signed-off-by: Mykola Kostenok \n> ---\n>  arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts | 49 +++++++++++++++++++++++++++\n>  arch/arm/boot/dts/aspeed-g5.dtsi              | 17 ++++++++++\n>  2 files changed, 66 insertions(+)\n> \n> diff --git a/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts b/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\n> index 0774959..d790927 100644\n> --- a/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\n> +++ b/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\n> @@ -139,3 +139,52 @@\n> >  \tstatus = \"okay\";\n>  };\n>  \n> +&pwm_tacho {\n> > +\tstatus = \"okay\";\n> > +\tpinctrl-names = \"default\";\n> > +\tpinctrl-0 = <&pinctrl_pwm0_default>;\n\nJust to confirm: One PWM pin is driving 8 fans?\n\n> > +\t#address-cells = <1>;\n> > +\t#size-cells = <0>;\n\nWe shouldn't need to re-specify either of these as they're done in the dtsi.\nHowever I have a question on #size-cells in the dtsi (see below).\n\n> > +\t#cooling-cells = <2>;\n> +\n> > +\tfan@0 {\n> > +\t\treg = <0x00>;\n> > +\t\tcooling-levels = /bits/ 8 <125 151 177 203 229 255>;\n\nThe bindings documentation says cooling-levels is a required property for each\nsubnode, yet only fan@0 is defining it.\n\nIs this somehow related to only muxing PWM0 above?\n\nRegardless I think you should meet the expectation of the bindings, even if the\ninformation is redundant.\n\n> > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x00>;\n> > +\t};\n> +\n> > +\tfan@1 {\n> > +\t\treg = <0x00>;\n\nReg should match the unit address in the node name, so what you've done here\nexpectations of the dts. However, it doesn't appear to give a compiler warning.\n\nOverall I think it's worth a comment.\n\nIn fact, I'm going to go out on a limb and claim the bindings are completely\nbackwards. You may use the one PWM to drive multiple fans, but you're never\ngoing to have multiple fans feed one tacho input. As such I'd have reg\nrepresent the tacho value, and aspeed,pwm-ch map the associated PWM channel.\nThis way we'd have:\n\n\t...\n\tfan@1 {\n\t\treg = <1>;\n\t\taspeed,pwm-ch = /bits/ 8 <0>;\n\t};\n\n\tfan@2 {\n\t\treg = <2>;\n\t\taspeed,pwm-ch = /bits/ 8 <0>;\n\t};\n\t...\n\nLooking at the datasheet we find that the hardware defines \"Tach Source\nRegisters\". Putting aside that the behaviour of the registers is pretty much\ninsane, this aligns exactly with the alternative bindings I suggested above:\nPWM inputs are configured for tach channels (tach channels dominate).\nEffectively my reg value would be an index into the fields of those registers.\n\nIt's annoying that the ship has probably sailed. We should start a conversation\nwith upstream, as your devicetree exposes the failure of the bindings.\n\n> > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x01>;\n> > +\t};\n> +\n> > +\tfan@2 {\n> > +\t\treg = <0x00>;\n> > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x02>;\n> > +\t};\n> +\n> > +\tfan@3 {\n> > +\t\treg = <0x00>;\n> > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x03>;\n> > +\t};\n> +\n> > +\tfan@4 {\n> > +\t\treg = <0x00>;\n> > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x04>;\n> > +\t};\n> +\n> > +\tfan@5 {\n> > +\t\treg = <0x00>;\n> > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x05>;\n> > +\t};\n> +\n> > +\tfan@6 {\n> > +\t\treg = <0x00>;\n> > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x06>;\n> > +\t};\n> +\n> > +\tfan@7 {\n> > +\t\treg = <0x00>;\n> > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x07>;\n> > +\t};\n> +};\n> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi\n> index 72b6638..4c012af 100644\n> --- a/arch/arm/boot/dts/aspeed-g5.dtsi\n> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi\n> @@ -40,6 +40,14 @@\n> >  \t\tserial4 = &uart5;\n> >  \t};\n>  \n> > +\tclocks {\n> > +\t\tpwm_tacho_fixed_clk: fixedclk {\n> > +\t\t\tcompatible = \"fixed-clock\";\n> > +\t\t\t#clock-cells = <0>;\n> > +\t\t\tclock-frequency = <24000000>;\n> > +\t\t};\n> > +\t};\n\nHappy to take this as it is what was done for the ast2400. Joel is getting the\nclock driver sorted out so hopefully we can remove it in the near future.\n\n> +\n> >  \tahb {\n> >  \t\tcompatible = \"simple-bus\";\n> >  \t\t#address-cells = <1>;\n> @@ -372,6 +380,15 @@\n> >  \t\t\t\t#size-cells = <1>;\n> >  \t\t\t\tranges = <0 0x1e78a000 0x1000>;\n> >  \t\t\t};\n> +\n> > > +\t\t\tpwm_tacho: pwm-tacho-controller@1e786000 {\n> > +\t\t\t\tcompatible = \"aspeed,ast2500-pwm-tacho\";\n> > +\t\t\t\t#address-cells = <1>;\n> > +\t\t\t\t#size-cells = <0>;\n\nThe bindings documentation claims #size-cells should be 1, however both the\nqanta dts and your patch set this to zero. The child nodes corroborate the\nvalue of 0 - we're specifying the PWM channel which has no need for a length.\nWe should update the bindings, though I'm not sure how happy upstream will be\nabout that. If I recall correctly Rob already quizzed you about why the\nbindings were being changed not long after they were applied. Still, better to\nbe right. Maybe we can rev the bindings and fix the PWM/tach mapping above?\n\nCheers for an interesting patch.\n\nAndrew\n\n> > +\t\t\t\treg = <0x1e786000 0x1000>;\n> > +\t\t\t\tclocks = <&pwm_tacho_fixed_clk>;\n> > +\t\t\t\tstatus = \"disabled\";\n> > +\t\t\t};\n> >  \t\t};\n> >  \t};\n>  };","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhLzw704Vz9t2x\n\tfor ;\n\tTue, 29 Aug 2017 18:15:40 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhLzw5fbYzDqZq\n\tfor ;\n\tTue, 29 Aug 2017 18:15:40 +1000 (AEST)","from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com\n\t[66.111.4.26])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhLzd2JtbzDqYV\n\tfor ; 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micalg=\"pgp-sha512\";\n\tprotocol=\"application/pgp-signature\";\n\tboundary=\"=-K8CoYt56yyOw6t8y5ME9\"","X-Mailer":"Evolution 3.22.6-1ubuntu1 ","Mime-Version":"1.0","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Ohad Oz , Vadim Pasternak ","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1759430,"web_url":"http://patchwork.ozlabs.org/comment/1759430/","msgid":"","list_archive_url":null,"date":"2017-08-29T15:05:47","subject":"RE: [PATCH linux dev-4.10 resend] dts: add aspeed-pwm-tacho to msn\n\tdts.","submitter":{"id":71635,"url":"http://patchwork.ozlabs.org/api/people/71635/","name":"Mykola Kostenok","email":"c_mykolak@mellanox.com"},"content":"> -----Original Message-----\r\n> From: Andrew Jeffery [mailto:andrew@aj.id.au]\r\n> Sent: Tuesday, August 29, 2017 11:15 AM\r\n> To: Mykola Kostenok ; Joel Stanley\r\n> ; openbmc@lists.ozlabs.org\r\n> Cc: Ohad Oz ; Vadim Pasternak\r\n> \r\n> Subject: Re: [PATCH linux dev-4.10 resend] dts: add aspeed-pwm-tacho to\r\n> msn dts.\r\n> \r\n> Hi Mykola,\r\n> \r\n> Sorry for taking so long to review this, thanks for the prompt with the\r\n> resend.\r\n> \r\n> Unfortunately the patch doesn't apply cleanly to dev-4.10 - can you please\r\n> rebase it and send a v2?\r\n\r\nHi, Andrew.\r\nYes, sure.\r\n\r\n> \r\n> I have some additional queries below.\r\n> \r\n> On Wed, 2017-08-23 at 10:33 +0300, Mykola Kostenok wrote:\r\n> > Add basic pwm-tacho-controller node to ast-g5 dtsi.\r\n> >\r\n> > Add pwm-tacho to aspeed-bmc-mellanox-msn.dts.\r\n> >\r\n> > > Signed-off-by: Mykola Kostenok \r\n> > ---\r\n> >  arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts | 49\r\n> > +++++++++++++++++++++++++++\r\n> >  arch/arm/boot/dts/aspeed-g5.dtsi              | 17 ++++++++++\r\n> >  2 files changed, 66 insertions(+)\r\n> >\r\n> > diff --git a/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\r\n> > b/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\r\n> > index 0774959..d790927 100644\r\n> > --- a/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\r\n> > +++ b/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\r\n> > @@ -139,3 +139,52 @@\r\n> > >  \tstatus = \"okay\";\r\n> >  };\r\n> >\r\n> > +&pwm_tacho {\r\n> > > +\tstatus = \"okay\";\r\n> > > +\tpinctrl-names = \"default\";\r\n> > > +\tpinctrl-0 = <&pinctrl_pwm0_default>;\r\n> \r\n> Just to confirm: One PWM pin is driving 8 fans?\r\n> \r\n\r\nYes, in Mellanox msn system open PWM driving 8 fans.\r\n\r\n> > > +\t#address-cells = <1>;\r\n> > > +\t#size-cells = <0>;\r\n> \r\n> We shouldn't need to re-specify either of these as they're done in the dtsi.\r\n> However I have a question on #size-cells in the dtsi (see below).\r\n> \r\n\r\nAcked.\r\n\r\n> > > +\t#cooling-cells = <2>;\r\n> > +\r\n> > > +\tfan@0 {\r\n> > > +\t\treg = <0x00>;\r\n> > > +\t\tcooling-levels = /bits/ 8 <125 151 177 203 229 255>;\r\n> \r\n> The bindings documentation says cooling-levels is a required property for\r\n> each subnode, yet only fan@0 is defining it.\r\n> \r\n> Is this somehow related to only muxing PWM0 above?\r\n> \r\n> Regardless I think you should meet the expectation of the bindings, even if\r\n> the information is redundant.\r\n\r\nOh, it's a mistake in docs. cooling-levels is not required - it's optional. \r\nWe tried to make separated node for pwm cooling-levels, but it was not acked by Rob Herring.\r\nNow it can be set only once for each PWM. As we use only PWM0 we set it once.\r\nAnd nothing bad happens with another systems without cooling-levels.\r\n\r\n> \r\n> > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x00>;\r\n> > > +\t};\r\n> > +\r\n> > > +\tfan@1 {\r\n> > > +\t\treg = <0x00>;\r\n> \r\n> Reg should match the unit address in the node name, so what you've done\r\n> here expectations of the dts. However, it doesn't appear to give a compiler\r\n> warning.\r\n> \r\n> Overall I think it's worth a comment.\r\n> \r\n> In fact, I'm going to go out on a limb and claim the bindings are completely\r\n> backwards. You may use the one PWM to drive multiple fans, but you're\r\n> never going to have multiple fans feed one tacho input. As such I'd have reg\r\n> represent the tacho value, and aspeed,pwm-ch map the associated PWM\r\n> channel.\r\n> This way we'd have:\r\n> \r\n> \t...\r\n> \tfan@1 {\r\n> \t\treg = <1>;\r\n> \t\taspeed,pwm-ch = /bits/ 8 <0>;\r\n> \t};\r\n> \r\n> \tfan@2 {\r\n> \t\treg = <2>;\r\n> \t\taspeed,pwm-ch = /bits/ 8 <0>;\r\n> \t};\r\n> \t...\r\n> \r\n> Looking at the datasheet we find that the hardware defines \"Tach Source\r\n> Registers\". Putting aside that the behaviour of the registers is pretty much\r\n> insane, this aligns exactly with the alternative bindings I suggested above:\r\n> PWM inputs are configured for tach channels (tach channels dominate).\r\n> Effectively my reg value would be an index into the fields of those registers.\r\n> \r\n> It's annoying that the ship has probably sailed. We should start a\r\n> conversation with upstream, as your devicetree exposes the failure of the\r\n> bindings.\r\n> \r\n\r\nWe just take it as it was. \r\n\r\n> > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x01>;\r\n> > > +\t};\r\n> > +\r\n> > > +\tfan@2 {\r\n> > > +\t\treg = <0x00>;\r\n> > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x02>;\r\n> > > +\t};\r\n> > +\r\n> > > +\tfan@3 {\r\n> > > +\t\treg = <0x00>;\r\n> > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x03>;\r\n> > > +\t};\r\n> > +\r\n> > > +\tfan@4 {\r\n> > > +\t\treg = <0x00>;\r\n> > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x04>;\r\n> > > +\t};\r\n> > +\r\n> > > +\tfan@5 {\r\n> > > +\t\treg = <0x00>;\r\n> > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x05>;\r\n> > > +\t};\r\n> > +\r\n> > > +\tfan@6 {\r\n> > > +\t\treg = <0x00>;\r\n> > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x06>;\r\n> > > +\t};\r\n> > +\r\n> > > +\tfan@7 {\r\n> > > +\t\treg = <0x00>;\r\n> > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x07>;\r\n> > > +\t};\r\n> > +};\r\n> > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi\r\n> > b/arch/arm/boot/dts/aspeed-g5.dtsi\r\n> > index 72b6638..4c012af 100644\r\n> > --- a/arch/arm/boot/dts/aspeed-g5.dtsi\r\n> > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi\r\n> > @@ -40,6 +40,14 @@\r\n> > >  \t\tserial4 = &uart5;\r\n> > >  \t};\r\n> >\r\n> > > +\tclocks {\r\n> > > +\t\tpwm_tacho_fixed_clk: fixedclk {\r\n> > > +\t\t\tcompatible = \"fixed-clock\";\r\n> > > +\t\t\t#clock-cells = <0>;\r\n> > > +\t\t\tclock-frequency = <24000000>;\r\n> > > +\t\t};\r\n> > > +\t};\r\n> \r\n> Happy to take this as it is what was done for the ast2400. Joel is getting the\r\n> clock driver sorted out so hopefully we can remove it in the near future.\r\n> \r\n\r\nOk.\r\n\r\n> > +\r\n> > >  \tahb {\r\n> > >  \t\tcompatible = \"simple-bus\";\r\n> > >  \t\t#address-cells = <1>;\r\n> > @@ -372,6 +380,15 @@\r\n> > >  \t\t\t\t#size-cells = <1>;\r\n> > >  \t\t\t\tranges = <0 0x1e78a000 0x1000>;\r\n> > >  \t\t\t};\r\n> > +\r\n> > > > +\t\t\tpwm_tacho: pwm-tacho-controller@1e786000 {\r\n> > > +\t\t\t\tcompatible = \"aspeed,ast2500-pwm-tacho\";\r\n> > > +\t\t\t\t#address-cells = <1>;\r\n> > > +\t\t\t\t#size-cells = <0>;\r\n> \r\n> The bindings documentation claims #size-cells should be 1, however both the\r\n> qanta dts and your patch set this to zero. The child nodes corroborate the\r\n> value of 0 - we're specifying the PWM channel which has no need for a\r\n> length.\r\n\r\nI think it’s a mistake in documentation.\r\n\r\n> We should update the bindings, though I'm not sure how happy upstream\r\n> will be about that. If I recall correctly Rob already quizzed you about why the\r\n> bindings were being changed not long after they were applied. Still, better to\r\n> be right. Maybe we can rev the bindings and fix the PWM/tach mapping\r\n> above?\r\n>\r\n> Cheers for an interesting patch.\r\n> \r\n> Andrew\r\n> \r\n\r\nIt's ok with us. Maybe it will be next step later.\r\n\r\nBest regards, Mykola Kostenok.\r\n\r\n\r\n> > > +\t\t\t\treg = <0x1e786000 0x1000>;\r\n> > > +\t\t\t\tclocks = <&pwm_tacho_fixed_clk>;\r\n> > > +\t\t\t\tstatus = \"disabled\";\r\n> > > +\t\t\t};\r\n> > >  \t\t};\r\n> > >  \t};\r\n> >  };","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhX5V564Fz9sRV\n\tfor ;\n\tWed, 30 Aug 2017 01:06:06 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhX5V3whZzDqlp\n\tfor ;\n\tWed, 30 Aug 2017 01:06:06 +1000 (AEST)","from EUR01-HE1-obe.outbound.protection.outlook.com\n\t(mail-he1eur01on0068.outbound.protection.outlook.com [104.47.0.68])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhX5H4zk0zDqkb\n\tfor ; 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"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com;\n\ts=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=tS5QoWRdjX+uavOww7ZMEYiBBqJS0cn6J4j1nNCImRc=;\n\tb=RnYrR6OFtPHP3aC+GSI0w4BkAcd2XFUcV9mODP0zKvaZVRGA8C8I/+cKfOrV7jLmqa8JHBTg2UnuVh/ENWUMQGUTVr55/h1GXyEj8Q4gNHqY39TV6dtMX/5YkQ7Ns2uF1S+RtRvCeG5gcB3ExYto9RylNkon/elW2UMsnWwvUSg=","From":"Mykola Kostenok ","To":"Andrew Jeffery , Joel Stanley ,\n\t\"openbmc@lists.ozlabs.org\" ","Subject":"RE: [PATCH linux dev-4.10 resend] dts: add aspeed-pwm-tacho to msn\n\tdts.","Thread-Topic":"[PATCH linux dev-4.10 resend] dts: add aspeed-pwm-tacho to msn\n\tdts.","Thread-Index":"AQHTG+IrhevFDggN5k+iy8kiqnKYj6KbBh0AgABgf+A=","Date":"Tue, 29 Aug 2017 15:05:47 +0000","Message-ID":"","References":"<20170823073313.1294-1-c_mykolak@mellanox.com>\n\t<1503994514.5933.8.camel@aj.id.au>","In-Reply-To":"<1503994514.5933.8.camel@aj.id.au>","Accept-Language":"ru-RU, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org; 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Joel Stanley\n> > > > ; openbmc@lists.ozlabs.org\n> > > > Cc: Ohad Oz ; Vadim Pasternak\n> > > > \n> > Subject: Re: [PATCH linux dev-4.10 resend] dts: add aspeed-pwm-tacho to\n> > msn dts.\n> > \n> > Hi Mykola,\n> > \n> > Sorry for taking so long to review this, thanks for the prompt with the\n> > resend.\n> > \n> > Unfortunately the patch doesn't apply cleanly to dev-4.10 - can you please\n> > rebase it and send a v2?\n> \n> Hi, Andrew.\n> Yes, sure.\n> \n> > \n> > I have some additional queries below.\n> > \n> > On Wed, 2017-08-23 at 10:33 +0300, Mykola Kostenok wrote:\n> > > Add basic pwm-tacho-controller node to ast-g5 dtsi.\n> > > \n> > > Add pwm-tacho to aspeed-bmc-mellanox-msn.dts.\n> > > \n> > > > Signed-off-by: Mykola Kostenok \n> > > \n> > > ---\n> > >  arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts | 49\n> > > +++++++++++++++++++++++++++\n> > >  arch/arm/boot/dts/aspeed-g5.dtsi              | 17 ++++++++++\n> > >  2 files changed, 66 insertions(+)\n> > > \n> > > diff --git a/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\n> > > b/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\n> > > index 0774959..d790927 100644\n> > > --- a/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\n> > > +++ b/arch/arm/boot/dts/aspeed-bmc-mellanox-msn.dts\n> > > @@ -139,3 +139,52 @@\n> > > >  \tstatus = \"okay\";\n> > > \n> > >  };\n> > > \n> > > +&pwm_tacho {\n> > > > > > > > +\tstatus = \"okay\";\n> > > > > > > > +\tpinctrl-names = \"default\";\n> > > > +\tpinctrl-0 = <&pinctrl_pwm0_default>;\n> > \n> > Just to confirm: One PWM pin is driving 8 fans?\n> > \n> \n> Yes, in Mellanox msn system open PWM driving 8 fans.\n> \n> > > > > > > > +\t#address-cells = <1>;\n> > > > +\t#size-cells = <0>;\n> > \n> > We shouldn't need to re-specify either of these as they're done in the dtsi.\n> > However I have a question on #size-cells in the dtsi (see below).\n> > \n> \n> Acked.\n> \n> > > > +\t#cooling-cells = <2>;\n> > > \n> > > +\n> > > > > > > > +\tfan@0 {\n> > > > > > > > +\t\treg = <0x00>;\n> > > > +\t\tcooling-levels = /bits/ 8 <125 151 177 203 229 255>;\n> > \n> > The bindings documentation says cooling-levels is a required property for\n> > > > each subnode, yet only fan@0 is defining it.\n> > \n> > Is this somehow related to only muxing PWM0 above?\n> > \n> > Regardless I think you should meet the expectation of the bindings, even if\n> > the information is redundant.\n> \n> Oh, it's a mistake in docs. cooling-levels is not required - it's optional. \n> We tried to make separated node for pwm cooling-levels, but it was not acked by Rob Herring.\n> Now it can be set only once for each PWM. As we use only PWM0 we set it once.\n> And nothing bad happens with another systems without cooling-levels.\n> \n> > \n> > > > > > > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x00>;\n> > > > +\t};\n> > > \n> > > +\n> > > > > > > > +\tfan@1 {\n> > > > +\t\treg = <0x00>;\n> > \n> > Reg should match the unit address in the node name, so what you've done\n> > here expectations of the dts. However, it doesn't appear to give a compiler\n> > warning.\n> > \n> > Overall I think it's worth a comment.\n> > \n> > In fact, I'm going to go out on a limb and claim the bindings are completely\n> > backwards. You may use the one PWM to drive multiple fans, but you're\n> > never going to have multiple fans feed one tacho input. As such I'd have reg\n> > represent the tacho value, and aspeed,pwm-ch map the associated PWM\n> > channel.\n> > This way we'd have:\n> > \n> > \t...\n> > > > \tfan@1 {\n> > > > \t\treg = <1>;\n> > > > \t\taspeed,pwm-ch = /bits/ 8 <0>;\n> > \t};\n> > \n> > > > \tfan@2 {\n> > > > \t\treg = <2>;\n> > > > \t\taspeed,pwm-ch = /bits/ 8 <0>;\n> > \t};\n> > \t...\n> > \n> > Looking at the datasheet we find that the hardware defines \"Tach Source\n> > Registers\". Putting aside that the behaviour of the registers is pretty much\n> > insane, this aligns exactly with the alternative bindings I suggested above:\n> > PWM inputs are configured for tach channels (tach channels dominate).\n> > Effectively my reg value would be an index into the fields of those registers.\n> > \n> > It's annoying that the ship has probably sailed. We should start a\n> > conversation with upstream, as your devicetree exposes the failure of the\n> > bindings.\n> > \n> \n> We just take it as it was. \n\nI understand. I'm discussing fans with upstream anyway, so I'll bring this\nissue up.\n\n> \n> > > > > > > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x01>;\n> > > > +\t};\n> > > \n> > > +\n> > > > > > > > +\tfan@2 {\n> > > > > > > > +\t\treg = <0x00>;\n> > > > > > > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x02>;\n> > > > +\t};\n> > > \n> > > +\n> > > > > > > > +\tfan@3 {\n> > > > > > > > +\t\treg = <0x00>;\n> > > > > > > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x03>;\n> > > > +\t};\n> > > \n> > > +\n> > > > > > > > +\tfan@4 {\n> > > > > > > > +\t\treg = <0x00>;\n> > > > > > > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x04>;\n> > > > +\t};\n> > > \n> > > +\n> > > > > > > > +\tfan@5 {\n> > > > > > > > +\t\treg = <0x00>;\n> > > > > > > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x05>;\n> > > > +\t};\n> > > \n> > > +\n> > > > > > > > +\tfan@6 {\n> > > > > > > > +\t\treg = <0x00>;\n> > > > > > > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x06>;\n> > > > +\t};\n> > > \n> > > +\n> > > > > > > > +\tfan@7 {\n> > > > > > > > +\t\treg = <0x00>;\n> > > > > > > > +\t\taspeed,fan-tach-ch = /bits/ 8 <0x07>;\n> > > > +\t};\n> > > \n> > > +};\n> > > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi\n> > > b/arch/arm/boot/dts/aspeed-g5.dtsi\n> > > index 72b6638..4c012af 100644\n> > > --- a/arch/arm/boot/dts/aspeed-g5.dtsi\n> > > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi\n> > > @@ -40,6 +40,14 @@\n> > > > > > > >  \t\tserial4 = &uart5;\n> > > > > > > >  \t};\n> > > > > > > > +\tclocks {\n> > > > > > > > +\t\tpwm_tacho_fixed_clk: fixedclk {\n> > > > > > > > +\t\t\tcompatible = \"fixed-clock\";\n> > > > > > > > +\t\t\t#clock-cells = <0>;\n> > > > > > > > +\t\t\tclock-frequency = <24000000>;\n> > > > > > > > +\t\t};\n> > > > +\t};\n> > \n> > Happy to take this as it is what was done for the ast2400. Joel is getting the\n> > clock driver sorted out so hopefully we can remove it in the near future.\n> > \n> \n> Ok.\n> \n> > > +\n> > > > > > > >  \tahb {\n> > > > > > > >  \t\tcompatible = \"simple-bus\";\n> > > >  \t\t#address-cells = <1>;\n> > > \n> > > @@ -372,6 +380,15 @@\n> > > > > > > >  \t\t\t\t#size-cells = <1>;\n> > > > > > > >  \t\t\t\tranges = <0 0x1e78a000 0x1000>;\n> > > >  \t\t\t};\n> > > \n> > > +\n> > > > > +\t\t\tpwm_tacho: pwm-tacho-controller@1e786000 {\n> > > > \n> > > > > > > > +\t\t\t\tcompatible = \"aspeed,ast2500-pwm-tacho\";\n> > > > > > > > +\t\t\t\t#address-cells = <1>;\n> > > > +\t\t\t\t#size-cells = <0>;\n> > \n> > The bindings documentation claims #size-cells should be 1, however both the\n> > qanta dts and your patch set this to zero. The child nodes corroborate the\n> > value of 0 - we're specifying the PWM channel which has no need for a\n> > length.\n> \n> I think it’s a mistake in documentation.\n\nRight; something we should fix. I'll include this with my upstream discussion\non fans.\n\nCheers,\n\nAndrew","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhtNN5mP2z9sN7\n\tfor ;\n\tWed, 30 Aug 2017 14:50:12 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhtNN4Cc3zDqJ8\n\tfor ;\n\tWed, 30 Aug 2017 14:50:12 +1000 (AEST)","from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com\n\t[66.111.4.26])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhtNC0sYmzDq5b\n\tfor ; Wed, 30 Aug 2017 14:50:03 +1000 (AEST)","from compute4.internal (compute4.nyi.internal [10.202.2.44])\n\tby mailout.nyi.internal (Postfix) with ESMTP id E4EA62139A;\n\tWed, 30 Aug 2017 00:50:00 -0400 (EDT)","from frontend2 ([10.202.2.161])\n\tby compute4.internal (MEProxy); Wed, 30 Aug 2017 00:50:00 -0400","from keelia (unknown [203.0.153.9])\n\tby mail.messagingengine.com (Postfix) with ESMTPA id 7968B24810;\n\tWed, 30 Aug 2017 00:49:58 -0400 (EDT)"],"Authentication-Results":["ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=aj.id.au header.i=@aj.id.au header.b=\"SaPwDKiW\";\n\tdkim=pass (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com header.b=\"JSoUq0Ku\"; \n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=aj.id.au header.i=@aj.id.au header.b=\"SaPwDKiW\";\n\tdkim=pass (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com header.b=\"JSoUq0Ku\"; \n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=aj.id.au header.i=@aj.id.au header.b=\"SaPwDKiW\";\n\tdkim=pass (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com\n\theader.b=\"JSoUq0Ku\"; dkim-atps=neutral"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc\n\t:content-type:date:from:in-reply-to:message-id:mime-version\n\t:references:subject:to:x-me-sender:x-me-sender:x-sasl-enc\n\t:x-sasl-enc; s=fm1; bh=Z5eL22DLARtgDXB41EvikyVi9/1fSNyPiNNR2kP04\n\tVY=; b=SaPwDKiW1HOVUVe8KBt199Z4nPNGTSpJ5c/K5ej6SHsv4eEVSN9/mb9mY\n\trJlgnoZnKOSPz9M6lh7RAYR8hF+ZdopnE8Ealr1CgzPaTcwEtiXHcbfqFGE6vNCn\n\tPDZzkTToKpWTMAwSsm0t0lZs5/GDMmZHKq5ZzFNBxPHKDXAQqU/hM32zW42fhvbg\n\tDkM9XhelmEH2BwEWOxZ4OL67yDMmallkfT5oawDFqxPliOzrbPeeUiLti9doFkoR\n\tHUM8stVrJDckSd+8iaFuh5g9sx0/2NVnsKHjfrGiiWZbd0Mn097eaqMBC7Dob8sN\n\tcHpbasiEdvUeXeeD5OcPHMm5ZFiGQ==","v=1; a=rsa-sha256; c=relaxed/relaxed; d=\n\tmessagingengine.com; h=cc:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to:x-me-sender\n\t:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=Z5eL22DLARtgDXB41E\n\tvikyVi9/1fSNyPiNNR2kP04VY=; b=JSoUq0Ku9GUBal5lDAT9YW5RJM1iIOXiQP\n\tNTLFd6F1SsE/hRUkgON4wRYKsuHtqXgete8qJDze6RcBZ64qVWMIs3sOtwneRMkX\n\taQIfsKNX9mF/MaTTpaaBaqC602TtSkCtYG+rsLEJRfXKvRGhZEtcFPO/1fc63Uqa\n\tWjy46fVlR9NBWY8buvuIkdRBPmCjgUa7l4m/2veuURZzpbWYG44H0X+ZAoAghp4X\n\tBmdnSjmw9e/dowu8BcLE/2oPzCqsfl/a4cGdw1h7iSG1ZM7jxeUGngHoObeqKRP3\n\tPH9B1auDfm9SlnSEtREGSl68uQToas9Osn5hUBkgtAFTsRyk2drQ=="],"X-ME-Sender":"","X-Sasl-enc":"gFv5NDMcm2oEfzZxPQywryWCcsy9G9GxeCI7MXp46SkW 1504068600","Message-ID":"<1504068592.5933.21.camel@aj.id.au>","Subject":"Re: [PATCH linux dev-4.10 resend] dts: add aspeed-pwm-tacho to msn\n\tdts.","From":"Andrew Jeffery ","To":"Mykola Kostenok , Joel Stanley , \n\t\"openbmc@lists.ozlabs.org\" ","Date":"Wed, 30 Aug 2017 14:19:52 +0930","In-Reply-To":"","References":"<20170823073313.1294-1-c_mykolak@mellanox.com>\n\t<1503994514.5933.8.camel@aj.id.au>\n\t","Content-Type":"multipart/signed; micalg=\"pgp-sha512\";\n\tprotocol=\"application/pgp-signature\";\n\tboundary=\"=-OD+hO/Jt07/4La8G5L7G\"","X-Mailer":"Evolution 3.22.6-1ubuntu1 ","Mime-Version":"1.0","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Ohad Oz , Vadim Pasternak ","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}}]