[{"id":1759552,"web_url":"http://patchwork.ozlabs.org/comment/1759552/","msgid":"<20170829171202.nnbai4i4vxln6pom@rob-hp-laptop>","list_archive_url":null,"date":"2017-08-29T17:12:02","subject":"Re: [PATCH 1/2] dt-bindings: aspeed-scu: Add clock and reset\n\tproperties","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring","email":"robh@kernel.org"},"content":"On Wed, Aug 23, 2017 at 03:39:56PM +0930, Joel Stanley wrote:\n> Signed-off-by: Joel Stanley \n> ---\n> Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 6 ++++++\n> 1 file changed, 6 insertions(+)\n\nAcked-by: Rob Herring \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170823060957.31167-1-joel@jms.id.au>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1762654,"web_url":"http://patchwork.ozlabs.org/comment/1762654/","msgid":"<20170904135247.cekcungzxig2r7tf@dell>","list_archive_url":null,"date":"2017-09-04T13:52:47","subject":"Re: [PATCH 1/2] dt-bindings: aspeed-scu: Add clock and reset\n\tproperties","submitter":{"id":12720,"url":"http://patchwork.ozlabs.org/api/people/12720/","name":"Lee Jones","email":"lee.jones@linaro.org"},"content":"On Wed, 23 Aug 2017, Joel Stanley wrote:\n\n> Signed-off-by: Joel Stanley \n> ---\n> Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 6 ++++++\n> 1 file changed, 6 insertions(+)\n\nApplied for v4.15.\n\n> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt\n> index 4fc5b83726d6..ce8cf0ec6279 100644\n> --- a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt\n> +++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt\n> @@ -9,10 +9,16 @@ Required properties:\n> \t\t\"aspeed,g5-scu\", \"syscon\", \"simple-mfd\"\n> \n> - reg:\t\tcontains the offset and length of the SCU memory region\n> +- #clock-cells: should be set to <1> - the system controller is also a\n> +\tclock provider\n> +- #reset-cells: should be set to <1> - the system controller is also a\n> +\treset line provider\n> \n> Example:\n> \n> syscon: syscon@1e6e2000 {\n> \tcompatible = \"aspeed,ast2400-scu\", \"syscon\", \"simple-mfd\";\n> \treg = <0x1e6e2000 0x1a8>;\n> +\t#clock-cells = <1>;\n> +\t#reset-cells = <1>;\n> };","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tMon, 04 Sep 2017 06:52:50 -0700 (PDT)","Date":"Mon, 4 Sep 2017 14:52:47 +0100","From":"Lee Jones ","To":"Joel Stanley ","Cc":"Rob Herring , Mark Rutland ,\n\tMichael Turquette ,\n\tStephen Boyd ,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, Andrew Jeffery ,\n\tBenjamin Herrenschmidt ,\n\tJeremy Kerr , Rick Altherr ,\n\tRyan Chen ","Subject":"Re: [PATCH 1/2] dt-bindings: aspeed-scu: Add clock and reset\n\tproperties","Message-ID":"<20170904135247.cekcungzxig2r7tf@dell>","References":"<20170823060957.31167-1-joel@jms.id.au>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<20170823060957.31167-1-joel@jms.id.au>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1768933,"web_url":"http://patchwork.ozlabs.org/comment/1768933/","msgid":"<1505446920.4080.13.camel@aj.id.au>","list_archive_url":null,"date":"2017-09-15T03:42:00","subject":"Re: [PATCH 2/2] clk: Add Aspeed G5 clock driver","submitter":{"id":68332,"url":"http://patchwork.ozlabs.org/api/people/68332/","name":"Andrew Jeffery","email":"andrew@aj.id.au"},"content":"On Wed, 2017-08-23 at 15:39 +0930, Joel Stanley wrote:\n> This driver supports the ast2500 and derivative BMC SoCs from Aspeed.\n> \n> All of the important clocks are supported, with most non-essential ones\n> also implemented where information is available. I am working with\n> Aspeed to clear up some of the missing information, including the\n> missing parent-sibling relationships.\n> \n> We need to know the rate of the apb clock in order to correctly program\n> the clocksource driver, so the apb and it's parents are created in the\n> CLK_OF_DECLARE_DRIVER callback.\n> \n> The rest of the clocks are created at normal driver probe time. I\n> followed the Gemini driver's lead with using the regmap where I could,\n> but also having a pointer to the base address for use with the common\n> clock callbacks.\n> \n> > Signed-off-by: Joel Stanley \n> ---\n>  drivers/clk/Kconfig                      |  12 +\n>  drivers/clk/Makefile                     |   1 +\n>  drivers/clk/clk-aspeed.c                 | 547 +++++++++++++++++++++++++++++++\n\nThe patch subject suggests the implementation is specific to the G5\nseries SoC, but the name of the driver is generic. How similar are the\nG4 and G5 clock devices? Is the intent to expand the implementation to\nalso cover the G4 series, or should this be renamed to something more\nspecific?\n\n>  include/dt-bindings/clock/aspeed-clock.h |  43 +++\n>  4 files changed, 603 insertions(+)\n>  create mode 100644 drivers/clk/clk-aspeed.c\n>  create mode 100644 include/dt-bindings/clock/aspeed-clock.h\n> \n> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig\n> index 8611b0de01a0..c16b8da0b4ca 100644\n> --- a/drivers/clk/Kconfig\n> +++ b/drivers/clk/Kconfig\n> @@ -135,6 +135,18 @@ config COMMON_CLK_GEMINI\n> >  \t  This driver supports the SoC clocks on the Cortina Systems Gemini\n> >  \t  platform, also known as SL3516 or CS3516.\n>  \n> +config COMMON_CLK_ASPEED\n\nThe answer to the question above should probably influence the name of\nthe config symbol.\n\nAndrew\n\n> +\tbool \"Clock driver for Aspeed BMC SoCs\"\n> > +\tdepends on ARCH_ASPEED || COMPILE_TEST\n> > +\tdefault ARCH_ASPEED\n> > +\tselect MFD_SYSCON\n> > +\tselect RESET_CONTROLLER\n> > +\t---help---\n> > +\t  This driver supports the SoC clocks on the Aspeed BMC platforms.\n> +\n> > +\t  Currently on the G5 series, such as the ast2500, is supported by\n> > +\t  this driver.\n> +\n>  config COMMON_CLK_S2MPS11\n> >  \ttristate \"Clock driver for S2MPS1X/S5M8767 MFD\"\n> >  \tdepends on MFD_SEC_CORE || COMPILE_TEST\n> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\n> index a625c002a810..58b440c31647 100644\n> --- a/drivers/clk/Makefile\n> +++ b/drivers/clk/Makefile\n> > @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_CLPS711X)\t\t+= clk-clps711x.o\n> >  obj-$(CONFIG_COMMON_CLK_CS2000_CP)\t+= clk-cs2000-cp.o\n> >  obj-$(CONFIG_ARCH_EFM32)\t\t+= clk-efm32gg.o\n> >  obj-$(CONFIG_COMMON_CLK_GEMINI)\t\t+= clk-gemini.o\n> > +obj-$(CONFIG_COMMON_CLK_ASPEED)\t\t+= clk-aspeed.o\n> >  obj-$(CONFIG_ARCH_HIGHBANK)\t\t+= clk-highbank.o\n> >  obj-$(CONFIG_COMMON_CLK_MAX77686)\t+= clk-max77686.o\n> >  obj-$(CONFIG_ARCH_MB86S7X)\t\t+= clk-mb86s7x.o\n> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c\n> new file mode 100644\n> index 000000000000..2c4483bdc3ca\n> --- /dev/null\n> +++ b/drivers/clk/clk-aspeed.c\n> @@ -0,0 +1,547 @@\n> +/*\n> + * Copyright 2017 IBM Corporation\n> + *\n> > + * Joel Stanley \n> + *\n> + * This program is free software; you can redistribute it and/or\n> + * modify it under the terms of the GNU General Public License\n> + * as published by the Free Software Foundation; either version\n> + * 2 of the License, or (at your option) any later version.\n> + */\n> +\n> +#define pr_fmt(fmt) \"clk-aspeed: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#include \n> +\n> > +#define ASPEED_RESET_CTRL\t0x04\n> > +#define ASPEED_CLK_SELECTION\t0x0c\n> > +#define ASPEED_CLK_STOP_CTRL\t0x0c\n> > +#define ASPEED_MPLL_PARAM\t0x20\n> > +#define ASPEED_HPLL_PARAM\t0x24\n> > +#define ASPEED_MISC_CTRL\t0x2c\n> > +#define ASPEED_STRAP\t\t0x70\n> +\n> +/* Globally visible clocks */\n> +static DEFINE_SPINLOCK(aspeed_clk_lock);\n> +\n> +/* Keeps track of all clocks */\n> +static struct clk_hw_onecell_data *aspeed_clk_data;\n> +\n> +/**\n> + * struct aspeed_gate_data - Aspeed gated clocks\n> + * @clock_idx: bit used to gate this clock in the clock register\n> + * @reset_idx: bit used to reset this IP in the reset register. -1 if no\n> + *             reset is required when enabling the clock\n> + * @name: the clock name\n> + * @parent_name: the name of the parent clock\n> + * @flags: standard clock framework flags\n> + */\n> +struct aspeed_gate_data {\n> > > +\tu8\t\tclock_idx;\n> > > +\ts8\t\treset_idx;\n> > > +\tconst char\t*name;\n> > > +\tconst char\t*parent_name;\n> > > +\tunsigned long\tflags;\n> +};\n> +\n> +/**\n> + * struct aspeed_clk_gate - Aspeed specific clk_gate structure\n> > + * @hw:\t\thandle between common and hardware-specific interfaces\n> > + * @reg:\tregister controlling gate\n> > + * @clock_idx:\tbit used to gate this clock in the clock register\n> > + * @reset_idx:\tbit used to reset this IP in the reset register. -1 if no\n> > + *\t\treset is required when enabling the clock\n> > + * @flags:\thardware-specific flags\n> > + * @lock:\tregister lock\n> + *\n> + * Some of the clocks in the Aspeed SoC must be put in reset before enabling.\n> + * This modified version of clk_gate allows an optional reset bit to be\n> + * specified.\n> + */\n> +struct aspeed_clk_gate {\n> > > +\tstruct clk_hw\thw;\n> > > +\tstruct regmap\t*map;\n> > > +\tu8\t\tclock_idx;\n> > > +\ts8\t\treset_idx;\n> > > +\tu8\t\tflags;\n> > > +\tspinlock_t\t*lock;\n> +};\n> +\n> +#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)\n> +\n> +/* TODO: ask Aspeed about the actual parent data */\n> +static const struct aspeed_gate_data aspeed_gates[] __initconst = {\n> > > > > +/*\t clk rst   name\t\t\tparent\t\tflags\t*/\n> > > > +\t{  0, -1, \"eclk-gate\",\t\t\"eclk\",\t\t0 }, /* Video Engine */\n> > > > +\t{  1,  7, \"gclk-gate\",\t\tNULL,\t\t0 }, /* 2D engine */\n> > > > +\t{  2, -1, \"mclk-gate\",\t\t\"mpll\",\t\tCLK_IS_CRITICAL }, /* SDRAM */\n> > > > +\t{  3,  6, \"vclk-gate\",\t\tNULL,\t\t0 }, /* Video Capture */\n> > > > +\t{  4, 10, \"bclk-gate\",\t\t\"bclk\",\t\t0 }, /* PCIe/PCI */\n> > > > +\t{  5, -1, \"dclk-gate\",\t\tNULL,\t\t0 }, /* DAC */\n> > > > +\t{  6, -1, \"refclk-gate\",\t\"clkin\",\tCLK_IS_CRITICAL },\n> > > > +\t{  7,  3, \"usb-port2-gate\",\tNULL,\t\t0 }, /* USB2.0 Host port 2 */\n> > > > +\t{  8,  5, \"lclk-gate\",\t\tNULL,\t\t0 }, /* LPC */\n> > > > +\t{  9, 15, \"usb-uhci-gate\",\tNULL,\t\t0 }, /* USB1.1 (requires port 2 enabled) */\n> > > > +\t{ 10, 13, \"d1clk-gate\",\t\tNULL,\t\t0 }, /* GFX CRT */\n> > +\t/* 11: reserved */\n> > +\t/* 12: reserved */\n> > > > +\t{ 13, 4,  \"yclk-gate\",\t\tNULL,\t\t0 }, /* HAC */\n> > > > +\t{ 14, 14, \"usb-port1-gate\",\tNULL,\t\t0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */\n> > > > +\t{ 15, -1, \"uart1clk-gate\",\t\"uart\",\t\t0 }, /* UART1 */\n> > > > +\t{ 16, -1, \"uart2clk-gate\",\t\"uart\",\t\t0 }, /* UART2 */\n> > > > +\t{ 17, -1, \"uart5clk-gate\",\t\"uart\",\t\t0 }, /* UART5 */\n> > +\t/* 18: reserved */\n> > > > +\t{ 19, -1, \"espiclk-gate\",\tNULL,\t\t0 }, /* eSPI */\n> > > > +\t{ 20, 11, \"mac1clk-gate\",\t\"clkin\",\t0 }, /* MAC1 */\n> > > > +\t{ 21, 12, \"mac2clk-gate\",\t\"clkin\",\t0 }, /* MAC2 */\n> > +\t/* 22: reserved */\n> > +\t/* 23: reserved */\n> > > > +\t{ 24, -1, \"rsaclk-gate\",\tNULL,\t\t0 }, /* RSA */\n> > > > +\t{ 25, -1, \"uart3clk-gate\",\t\"uart\",\t\t0 }, /* UART3 */\n> > > > +\t{ 26, -1, \"uart4clk-gate\",\t\"uart\",\t\t0 }, /* UART4 */\n> > > > +\t{ 27, 16, \"sdclk-gate\",\t\tNULL,\t\t0 }, /* SDIO/SD */\n> > > > +\t{ 28, -1, \"lhclk-gate\",\t\t\"lhclk\",\t0 }, /* LPC master/LPC+ */\n> > +\t/* 29: reserved */\n> > +\t/* 30: reserved */\n> > +\t/* 31: reserved */\n> +};\n> +\n> +static const char * const eclk_parents[] = {\"d1pll\", \"hpll\", \"mpll\"};\n> +\n> +static const struct clk_div_table aspeed_mac_div_table[] = {\n> > +\t{ 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */\n> > +\t{ 0x1, 4 },\n> > +\t{ 0x2, 6 },\n> > +\t{ 0x3, 8 },\n> > +\t{ 0x4, 10 },\n> > +\t{ 0x5, 12 },\n> > +\t{ 0x6, 14 },\n> > +\t{ 0x7, 16 },\n> > +\t{ 0 }\n> +};\n> +\n> +static const struct clk_div_table aspeed_div_table[] = {\n> > +\t{ 0x0, 4 },\n> > +\t{ 0x1, 8 },\n> > +\t{ 0x2, 12 },\n> > +\t{ 0x3, 16 },\n> > +\t{ 0x4, 20 },\n> > +\t{ 0x5, 24 },\n> > +\t{ 0x6, 28 },\n> > +\t{ 0x7, 32 },\n> > +\t{ 0 }\n> +};\n> +\n> +static int aspeed_clk_enable(struct clk_hw *hw)\n> +{\n> > +\tstruct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);\n> > +\tunsigned long flags;\n> > +\tu32 clk = BIT(gate->clock_idx);\n> > +\tu32 rst = BIT(gate->reset_idx);\n> +\n> > +\tspin_lock_irqsave(gate->lock, flags);\n> +\n> > +\tif (gate->reset_idx >= 0) {\n> > +\t\t/* Put IP in reset */\n> > +\t\tregmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);\n> +\n> > +\t\t/* Delay 100us */\n> > +\t\tudelay(100);\n> > +\t}\n> +\n> > +\t/* Enable clock */\n> > +\tregmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, 0);\n> +\n> > +\tif (gate->reset_idx >= 0) {\n> > +\t\t/* Delay 10ms */\n> > +\t\t/* TODO: can we sleep here? */\n> > +\t\tmsleep(10);\n> +\n> > +\t\t/* Take IP out of reset */\n> > +\t\tregmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);\n> > +\t}\n> +\n> > +\tspin_unlock_irqrestore(gate->lock, flags);\n> +\n> > +\treturn 0;\n> +}\n> +\n> +static void aspeed_clk_disable(struct clk_hw *hw)\n> +{\n> > +\tstruct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);\n> > +\tunsigned long flags;\n> > +\tu32 clk = BIT(gate->clock_idx);\n> +\n> > +\tspin_lock_irqsave(gate->lock, flags);\n> +\n> > +\t/* Disable clock */\n> > +\tregmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, clk);\n> +\n> > +\tspin_unlock_irqrestore(gate->lock, flags);\n> +}\n> +\n> +static int aspeed_clk_is_enabled(struct clk_hw *hw)\n> +{\n> > +\tstruct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);\n> > +\tu32 clk = BIT(gate->clock_idx);\n> > +\tu32 reg;\n> +\n> > +\tregmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);\n> +\n> > +\treturn (reg & clk) ? 0 : 1;\n> +}\n> +\n> +static const struct clk_ops aspeed_clk_gate_ops = {\n> > +\t.enable = aspeed_clk_enable,\n> > +\t.disable = aspeed_clk_disable,\n> > +\t.is_enabled = aspeed_clk_is_enabled,\n> +};\n> +\n> +/**\n> + * struct aspeed_reset - Aspeed reset controller\n> + * @map: regmap to access the containing system controller\n> + * @rcdev: reset controller device\n> + */\n> +struct aspeed_reset {\n> > > +\tstruct regmap\t\t\t*map;\n> > > +\tstruct reset_controller_dev\trcdev;\n> +};\n> +\n> +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)\n> +\n> +static const u8 aspeed_resets[] = {\n> > +\t25, /* x-dma */\n> > +\t24, /* mctp */\n> > +\t23, /* adc */\n> > +\t22, /* jtag-master */\n> > +\t18, /* mic */\n> > +\t 9, /* pwm */\n> > +\t 8, /* pci-vga */\n> > +\t 2, /* i2c */\n> > +\t 1, /* ahb */\n> +};\n> +\n> +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,\n> > +\t\t\t\t unsigned long id)\n> +{\n> > +\tstruct aspeed_reset *ar = to_aspeed_reset(rcdev);\n> > +\tu32 rst = BIT(aspeed_resets[id]);\n> +\n> > +\treturn regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);\n> +}\n> +\n> +static int aspeed_reset_assert(struct reset_controller_dev *rcdev,\n> > +\t\t\t       unsigned long id)\n> +{\n> > +\tstruct aspeed_reset *ar = to_aspeed_reset(rcdev);\n> > +\tu32 rst = BIT(aspeed_resets[id]);\n> +\n> > +\treturn regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);\n> +}\n> +\n> +static int aspeed_reset_status(struct reset_controller_dev *rcdev,\n> > +\t\t\t       unsigned long id)\n> +{\n> > +\tstruct aspeed_reset *ar = to_aspeed_reset(rcdev);\n> > +\tu32 val, rst = BIT(aspeed_resets[id]);\n> > +\tint ret;\n> +\n> > +\tret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);\n> > +\tif (ret)\n> > +\t\treturn ret;\n> +\n> > +\treturn !!(val & rst);\n> +}\n> +\n> +static const struct reset_control_ops aspeed_reset_ops = {\n> > +\t.assert = aspeed_reset_assert,\n> > +\t.deassert = aspeed_reset_deassert,\n> > +\t.status = aspeed_reset_status,\n> +};\n> +\n> +static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,\n> > +\t\tconst char *name, const char *parent_name, unsigned long flags,\n> > +\t\tstruct regmap *map, u8 clock_idx, u8 reset_idx,\n> > +\t\tu8 clk_gate_flags, spinlock_t *lock)\n> +{\n> > +\tstruct aspeed_clk_gate *gate;\n> > +\tstruct clk_init_data init;\n> > +\tstruct clk_hw *hw;\n> > +\tint ret;\n> +\n> > +\tgate = kzalloc(sizeof(*gate), GFP_KERNEL);\n> > +\tif (!gate)\n> > +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> > +\tinit.name = name;\n> > +\tinit.ops = &aspeed_clk_gate_ops;\n> > +\tinit.flags = flags | CLK_IS_BASIC;\n> > +\tinit.parent_names = parent_name ? &parent_name : NULL;\n> > +\tinit.num_parents = parent_name ? 1 : 0;\n> +\n> > +\tgate->map = map;\n> > +\tgate->clock_idx = clock_idx;\n> > +\tgate->reset_idx = reset_idx;\n> > +\tgate->flags = clk_gate_flags;\n> > +\tgate->lock = lock;\n> > +\tgate->hw.init = &init;\n> +\n> > +\thw = &gate->hw;\n> > +\tret = clk_hw_register(dev, hw);\n> > +\tif (ret) {\n> > +\t\tkfree(gate);\n> > +\t\thw = ERR_PTR(ret);\n> > +\t}\n> +\n> > +\treturn hw;\n> +}\n> +\n> +static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n> +{\n> > +\tunsigned int mult, div;\n> +\n> > +\tif (val & BIT(20)) {\n> > +\t\t/* Pass through mode */\n> > +\t\tmult = div = 1;\n> > +\t} else {\n> > +\t\t/* F = clkin * [(M+1) / (N+1)] / (P + 1) */\n> > +\t\tu32 p = (val >> 13) & 0x3f;\n> > +\t\tu32 m = (val >> 5) & 0xff;\n> > +\t\tu32 n = val & 0x1f;\n> +\n> > +\t\tmult = (m + 1) / (n + 1);\n> > +\t\tdiv = p + 1;\n> > +\t}\n> +\n> > +\treturn clk_hw_register_fixed_factor(NULL, name, \"clkin\", 0,\n> > +\t\t\tmult, div);\n> +}\n> +\n> +static int __init aspeed_clk_probe(struct platform_device *pdev)\n> +{\n> > +\tstruct device *dev = &pdev->dev;\n> > +\tstruct aspeed_reset *ar;\n> > +\tvoid __iomem *scu_base;\n> > +\tstruct resource *res;\n> > +\tstruct regmap *map;\n> > +\tstruct clk_hw *hw;\n> > +\tu32 val, rate;\n> > +\tint i, ret;\n> +\n> > +\tar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);\n> > +\tif (!ar)\n> > +\t\treturn -ENOMEM;\n> +\n> > +\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> > +\tscu_base = devm_ioremap_resource(dev, res);\n> > +\tif (IS_ERR(scu_base))\n> > +\t\treturn PTR_ERR(scu_base);\n> +\n> > +\tmap = syscon_node_to_regmap(dev->of_node);\n> > +\tif (IS_ERR(map)) {\n> > +\t\tdev_err(dev, \"no syscon regmap\\n\");\n> > +\t\treturn PTR_ERR(map);\n> > +\t}\n> +\n> > +\tar->map = map;\n> > +\tar->rcdev.owner = THIS_MODULE;\n> > +\tar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);\n> > +\tar->rcdev.ops = &aspeed_reset_ops;\n> > +\tar->rcdev.of_node = dev->of_node;\n> +\n> > +\tret = devm_reset_controller_register(dev, &ar->rcdev);\n> > +\tif (ret) {\n> > +\t\tdev_err(dev, \"could not register reset controller\\n\");\n> > +\t\treturn ret;\n> > +\t}\n> +\n> > +\t/* UART clock div13 setting */\n> > +\tregmap_read(map, ASPEED_MISC_CTRL, &val);\n> > +\tif (val & BIT(12))\n> > +\t\trate = 24000000 / 13;\n> > +\telse\n> > +\t\trate = 24000000;\n> > +\t/* TODO: Find the parent data for the uart clock */\n> > +\thw = clk_hw_register_fixed_rate(NULL, \"uart\", NULL, 0, rate);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_UART] = hw;\n> +\n> > +\t/*\n> > +\t * Memory controller (M-PLL) PLL. This clock is configured by the\n> > +\t * bootloader, and is exposed to Linux as a read-only clock rate.\n> > +\t */\n> > +\tregmap_read(map, ASPEED_MPLL_PARAM, &val);\n> > > +\taspeed_clk_data->hws[ASPEED_CLK_MPLL] =\taspeed_calc_pll(\"mpll\", val);\n> +\n> > +\t/* SD/SDIO clock divider (TODO: There's a gate too) */\n> > +\thw = clk_hw_register_divider_table(NULL, \"sdio\", \"hpll\", 0,\n> > +\t\t\tscu_base + ASPEED_CLK_SELECTION, 12, 3, 0,\n> > +\t\t\taspeed_div_table,\n> > +\t\t\t&aspeed_clk_lock);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;\n> +\n> > +\t/* MAC AHB bus clock divider */\n> > +\thw = clk_hw_register_divider_table(NULL, \"mac\", \"hpll\", 0,\n> > +\t\t\tscu_base + ASPEED_CLK_SELECTION, 16, 3, 0,\n> > +\t\t\taspeed_mac_div_table,\n> > +\t\t\t&aspeed_clk_lock);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;\n> +\n> > +\t/* LPC Host (LHCLK) clock divider */\n> > +\thw = clk_hw_register_divider_table(NULL, \"lhclk\", \"hpll\", 0,\n> > +\t\t\tscu_base + ASPEED_CLK_SELECTION, 20, 3, 0,\n> > +\t\t\taspeed_div_table,\n> > +\t\t\t&aspeed_clk_lock);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;\n> +\n> > +\t/* Video Engine (ECLK) mux and clock divider */\n> > +\thw = clk_hw_register_mux(NULL, \"eclk_mux\",\n> > +\t\t\teclk_parents, ARRAY_SIZE(eclk_parents), 0,\n> > +\t\t\tscu_base + ASPEED_CLK_SELECTION, 2, 2,\n> > +\t\t\t0, &aspeed_clk_lock);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;\n> > +\thw = clk_hw_register_divider_table(NULL, \"eclk\", \"eclk_mux\", 0,\n> > +\t\t\tscu_base + ASPEED_CLK_SELECTION, 20, 3, 0,\n> > +\t\t\taspeed_div_table,\n> > +\t\t\t&aspeed_clk_lock);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;\n> +\n> > +\t/* P-Bus (BCLK) clock divider */\n> > +\thw = clk_hw_register_divider_table(NULL, \"bclk\", \"hpll\", 0,\n> > +\t\t\tscu_base + ASPEED_CLK_SELECTION, 0, 2, 0,\n> > +\t\t\taspeed_div_table,\n> > +\t\t\t&aspeed_clk_lock);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;\n> +\n> > +\t/* There are a number of clocks that not included in this driver as\n> > +\t * more information is required:\n> > +\t *   D2-PLL\n> > +\t *   D-PLL\n> > +\t *   YCLK\n> > +\t *   RGMII\n> > +\t *   RMII\n> > +\t *   UART[1..5] clock source mux\n> > +\t */\n> +\n> > +\tfor (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {\n> > +\t\tconst struct aspeed_gate_data *gd;\n> +\n> > +\t\tgd = &aspeed_gates[i];\n> > +\t\taspeed_clk_data->hws[ASPEED_CLK_GATES + i] =\n> > +\t\t\taspeed_clk_hw_register_gate(NULL, gd->name,\n> > +\t\t\t\t\t     gd->parent_name,\n> > +\t\t\t\t\t     gd->flags,\n> > +\t\t\t\t\t     map,\n> > +\t\t\t\t\t     gd->clock_idx,\n> > +\t\t\t\t\t     gd->reset_idx,\n> > +\t\t\t\t\t     CLK_GATE_SET_TO_DISABLE,\n> > +\t\t\t\t\t     &aspeed_clk_lock);\n> > +\t}\n> +\n> > +\treturn 0;\n> +};\n> +\n> +static const struct of_device_id aspeed_clk_dt_ids[] = {\n> > +\t{ .compatible = \"aspeed,ast2500-scu\", },\n> > +\t{ },\n> +};\n> +\n> +static struct platform_driver aspeed_clk_driver = {\n> > +\t.probe  = aspeed_clk_probe,\n> > +\t.driver = {\n> > +\t\t.name = \"aspeed-clk\",\n> > +\t\t.of_match_table = aspeed_clk_dt_ids,\n> > +\t\t.suppress_bind_attrs = true,\n> > +\t},\n> +};\n> +builtin_platform_driver(aspeed_clk_driver);\n> +\n> +static void __init aspeed_cc_init(struct device_node *np)\n> +{\n> > +\tstruct regmap *map;\n> > +\tunsigned long freq;\n> > +\tstruct clk_hw *hw;\n> > +\tunsigned int div;\n> > +\tu32 val;\n> > +\tint ret;\n> > +\tint i;\n> +\n> > +\taspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) +\n> > +\t\t\tsizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS,\n> > +\t\t\tGFP_KERNEL);\n> > +\tif (!aspeed_clk_data)\n> > +\t\treturn;\n> +\n> > +\t/*\n> > +\t * This way all clock fetched before the platform device probes,\n> > +\t * except those we assign here for early use, will be deferred.\n> > +\t */\n> > +\tfor (i = 0; i < ASPEED_NUM_CLKS; i++)\n> > +\t\taspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);\n> +\n> > +\tmap = syscon_node_to_regmap(np);\n> > +\tif (IS_ERR(map)) {\n> > +\t\tpr_err(\"no syscon regmap\\n\");\n> > +\t\treturn;\n> > +\t}\n> > +\t/*\n> > +\t * We check that the regmap works on this very first access,\n> > +\t * but as this is an MMIO-backed regmap, subsequent regmap\n> > +\t * access is not going to fail and we skip error checks from\n> > +\t * this point.\n> > +\t */\n> > +\tret = regmap_read(map, ASPEED_STRAP, &val);\n> > +\tif (ret) {\n> > +\t\tpr_err(\"failed to read strapping register\\n\");\n> > +\t\treturn;\n> > +\t}\n> +\n> > +\t/* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */\n> > +\tif (val & BIT(23))\n> > +\t\tfreq = 25000000;\n> > +\telse\n> > +\t\tfreq = 24000000;\n> > +\thw = clk_hw_register_fixed_rate(NULL, \"clkin\", NULL, 0, freq);\n> > +\tpr_debug(\"clkin @%lu MHz\\n\", freq / 1000000);\n> +\n> > +\t/*\n> > +\t * High-speed PLL clock derived from the crystal. This the CPU clock,\n> > +\t * and we assume that it is enabled\n> > +\t */\n> > +\tregmap_read(map, ASPEED_HPLL_PARAM, &val);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_calc_pll(\"hpll\", val);\n> +\n> > +\t/* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/\n> > +\tregmap_read(map, ASPEED_STRAP, &val);\n> > +\tval = (val >> 9) & 0x7;\n> > +\tWARN_ON(val == 0);\n> > +\tdiv = 2 * (val + 1);\n> > +\thw = clk_hw_register_fixed_factor(NULL, \"ahb\", \"hpll\", 0, 1, div);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;\n> +\n> > +\t/* APB clock clock selection register SCU08 (aka PCLK) */\n> > +\tregmap_read(map, ASPEED_CLK_SELECTION, &val);\n> > +\tval = (val >> 23) & 0x7;\n> > +\tdiv = 4 * (val + 1);\n> > +\thw = clk_hw_register_fixed_factor(NULL, \"apb\", \"hpll\", 0, 1, div);\n> > +\taspeed_clk_data->hws[ASPEED_CLK_APB] = hw;\n> +\n> > +\taspeed_clk_data->num = ASPEED_NUM_CLKS;\n> > +\tret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);\n> > +\tif (ret)\n> > +\t\tpr_err(\"failed to add DT provider: %d\\n\", ret);\n> +};\n> +CLK_OF_DECLARE_DRIVER(aspeed_cc, \"aspeed,ast2500-scu\", aspeed_cc_init);\n> diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h\n> new file mode 100644\n> index 000000000000..afe06b77562d\n> --- /dev/null\n> +++ b/include/dt-bindings/clock/aspeed-clock.h\n> @@ -0,0 +1,43 @@\n> +#ifndef DT_BINDINGS_ASPEED_CLOCK_H\n> +#define DT_BINDINGS_ASPEED_CLOCK_H\n> +\n> > +#define ASPEED_NUM_CLKS\t34\n> +\n> > +#define ASPEED_CLK_HPLL\t\t\t0\n> > +#define ASPEED_CLK_AHB\t\t\t1\n> > +#define ASPEED_CLK_APB\t\t\t2\n> > +#define ASPEED_CLK_UART\t\t\t3\n> > +#define ASPEED_CLK_SDIO\t\t\t4\n> > +#define ASPEED_CLK_ECLK\t\t\t5\n> > +#define ASPEED_CLK_ECLK_MUX\t\t6\n> > +#define ASPEED_CLK_LHCLK\t\t7\n> > +#define ASPEED_CLK_MAC\t\t\t8\n> > +#define ASPEED_CLK_BCLK\t\t\t9\n> > +#define ASPEED_CLK_MPLL\t\t\t10\n> > +#define ASPEED_CLK_GATES\t\t11\n> > +#define ASPEED_CLK_GATE_ECLK\t\t(0 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_GCLK\t\t(1 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_MCLK\t\t(2 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_VCLK\t\t(3 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_BCLK\t\t(4 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_DCLK\t\t(5 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_REFCLK\t\t(6 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_USBPORT2CLK\t(7 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_LCLK\t\t(8 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_USBUHCICLK\t(9 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_D1CLK\t\t(10 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_YCLK\t\t(11 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_USBPORT1CLK\t(12 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_UART1CLK\t(13 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_UART2CLK\t(14 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_UART5CLK\t(15 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_ESPICLK\t\t(16 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_MAC1CLK\t\t(17 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_MAC2CLK\t\t(18 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_RSACLK\t\t(19 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_UART3CLK\t(20 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_UART4CLK\t(21 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_SDCLKCLK\t(22 + ASPEED_CLK_GATES)\n> > +#define ASPEED_CLK_GATE_LHCCLK\t\t(23 + ASPEED_CLK_GATES)\n> +\n> +#endif","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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micalg=\"pgp-sha512\";\n\tprotocol=\"application/pgp-signature\";\n\tboundary=\"=-oi4bOF759sUmL9CyXzeY\"","X-Mailer":"Evolution 3.22.6-1ubuntu1 ","Mime-Version":"1.0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770149,"web_url":"http://patchwork.ozlabs.org/comment/1770149/","msgid":"","list_archive_url":null,"date":"2017-09-18T13:19:44","subject":"Re: [PATCH 2/2] clk: Add Aspeed G5 clock driver","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Fri, Sep 15, 2017 at 1:12 PM, Andrew Jeffery wrote:\n> On Wed, 2017-08-23 at 15:39 +0930, Joel Stanley wrote:\n>> This driver supports the ast2500 and derivative BMC SoCs from Aspeed.\n>>\n>> All of the important clocks are supported, with most non-essential ones\n>> also implemented where information is available. I am working with\n>> Aspeed to clear up some of the missing information, including the\n>> missing parent-sibling relationships.\n>>\n>> We need to know the rate of the apb clock in order to correctly program\n>> the clocksource driver, so the apb and it's parents are created in the\n>> CLK_OF_DECLARE_DRIVER callback.\n>>\n>> The rest of the clocks are created at normal driver probe time. I\n>> followed the Gemini driver's lead with using the regmap where I could,\n>> but also having a pointer to the base address for use with the common\n>> clock callbacks.\n>>\n>> > Signed-off-by: Joel Stanley \n>> ---\n>> drivers/clk/Kconfig | 12 +\n>> drivers/clk/Makefile | 1 +\n>> drivers/clk/clk-aspeed.c | 547 +++++++++++++++++++++++++++++++\n>\n> The patch subject suggests the implementation is specific to the G5\n> series SoC, but the name of the driver is generic. How similar are the\n> G4 and G5 clock devices? Is the intent to expand the implementation to\n> also cover the G4 series, or should this be renamed to something more\n> specific?\n\nThe intent is to cover the G4 platforms with the same driver. I sent\nthis version along early to get feedback on the structure.\n\nAs it turns out, it was simple to get the G4 going with the same code.\nI'll send a v2 in the next day or so.\n\nCheers,\n\nJoel\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ghdkIgcf\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwmp22DCGz9s7c\n\tfor ;\n\tMon, 18 Sep 2017 23:20:10 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753226AbdIRNUI (ORCPT\n\t);\n\tMon, 18 Sep 2017 09:20:08 -0400","from mail-lf0-f67.google.com ([209.85.215.67]:35891 \"EHLO\n\tmail-lf0-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752368AbdIRNUH (ORCPT\n\t); Mon, 18 Sep 2017 09:20:07 -0400","by mail-lf0-f67.google.com with SMTP id l196so290748lfl.3;\n\tMon, 18 Sep 2017 06:20:06 -0700 (PDT)","by 10.25.103.82 with HTTP; Mon, 18 Sep 2017 06:19:44 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:sender:in-reply-to:references:from:date:message-id\n\t:subject:to:cc;\n\tbh=OtKNzBNJGhgHqgGMopBw9KBc5Bp1VSwHtS4cbrzGSS8=;\n\tb=ghdkIgcfazh5I3uu3OuknuWt0X8O6eOjI2X5VAO2qgXYu2fuSxXKKtCc9eHbZT5AEd\n\tq9YZ2kZImEDODsrC7/6QZ0gHCe5gIleqIBhC2HGjeEEjCDt2g1FAFg3RGnHV2cXSa9mi\n\tfYOia7wcWhohv1P4thpffrH51qagXmNO7hwB8sJIhNtk6gU+Xu2ZxAoIpyTtXIDHBUZE\n\twN4vD7e5H7P9aM+wsLal15lBNrjd5XRnfwmQBFZbr+aUtb/U8dFdUja3SZkfrX8tSsAR\n\tbZq4hu8Uqi7uMFTj38L6EIryneby4Pd8vsoUAxOm8aMoPUK+aj0OIxDWkZLF9E3VNUSq\n\tSaVw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:sender:in-reply-to:references:from\n\t:date:message-id:subject:to:cc;\n\tbh=OtKNzBNJGhgHqgGMopBw9KBc5Bp1VSwHtS4cbrzGSS8=;\n\tb=D+nl3KKdQYM9xW1KgMIuikSMf4kGODMZ5nq12V2AROmYC2xDxEi9f2Qjrs08+4ycWf\n\txnrzNC2ckWSjzI4MHVp1n9vPQ8y95dgF0JWDvTfqqyV5/Ee101EFXqkwiIjPh36bq61D\n\twv07/eykw1zOCEEXc/UgU6cu8U4AJlyTZgGjvoT2EOmH4src92GGy3P0+AzJOuskh9bW\n\tg9rkvdZx/XMCWuX9G5aKJ80lf2h0/63Ukyk4PZ7VG+pHWxifPRz3GuDWFp6/WQBn+ZwK\n\t/UKT9AZGMeAGMT2xiOO8tALbVce6AjyKQpj6D98EUPGh+VrNSqyAG8twinjZYbCQqzd0\n\tDCvQ==","X-Gm-Message-State":"AHPjjUiKAu3qkAPhprkyhhxhpAWZG7RS7fnZcTYFks8OtvghUVZQ42qT\n\tWTg+qge6/siQljOWpPXcfGqba3Cr4Ub/mfN1iUk=","X-Google-Smtp-Source":"ADKCNb4+Sn0oR55UrMd91n2uy3XvvYbx4xAfsHYIkI/cnoNY61KAsoMbijlvx4K26bqzEAX8wx0sZnw53Pmx0Xkuk60=","X-Received":"by 10.46.27.1 with SMTP id b1mr13548740ljb.36.1505740805395; Mon,\n\t18 Sep 2017 06:20:05 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1505446920.4080.13.camel@aj.id.au>","References":"<20170823060957.31167-1-joel@jms.id.au>\n\t<20170823060957.31167-2-joel@jms.id.au>\n\t<1505446920.4080.13.camel@aj.id.au>","From":"Joel Stanley ","Date":"Mon, 18 Sep 2017 22:49:44 +0930","X-Google-Sender-Auth":"6oOh4PU01yhF8fR98g5-MMw9LKA","Message-ID":"","Subject":"Re: [PATCH 2/2] clk: Add Aspeed G5 clock driver","To":"Andrew Jeffery ","Cc":"Lee Jones , Rob Herring ,\n\tMark Rutland ,\n\tMichael Turquette ,\n\tStephen Boyd ,\n\tdevicetree ,\n\tLinux Kernel Mailing List ,\n\tlinux-clk@vger.kernel.org,\n\tBenjamin Herrenschmidt ,\n\tJeremy Kerr , Rick Altherr ,\n\tRyan Chen ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]