[{"id":1752753,"web_url":"http://patchwork.ozlabs.org/comment/1752753/","msgid":"","list_archive_url":null,"date":"2017-08-21T12:03:13","subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","submitter":{"id":70239,"url":"http://patchwork.ozlabs.org/api/people/70239/","name":"Suresh Gupta","email":"suresh.gupta@nxp.com"},"content":"Hi York, \n\nCan I delegate this patch to you? Delegate to Jagan (SPI Maintainer) delays the acceptance process. \n\nThanks \nSuresH\n\n> -----Original Message-----\n> From: Suresh Gupta [mailto:suresh.gupta@nxp.com]\n> Sent: Monday, August 21, 2017 3:56 PM\n> To: u-boot@lists.denx.de\n> Cc: York Sun ; jagan@openedev.com; Prabhakar Kushwaha\n> ; Suresh Gupta \n> Subject: [PATCH] spi: fsl_qspi: Add controller busy check before new spi\n> operation\n> \n> It is recommended to check either controller is free to take new spi action. The\n> IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode\n> respectively.\n> And the BUSY bit indicates that the controller is currently busy handling a\n> transaction to an external flash device\n> \n> Signed-off-by: Suresh Gupta \n> ---\n> drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++ drivers/spi/fsl_qspi.h\n> | 4 ++++\n> 2 files changed, 30 insertions(+)\n> \n> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 1dfa89a..69e9712\n> 100644\n> --- a/drivers/spi/fsl_qspi.c\n> +++ b/drivers/spi/fsl_qspi.c\n> @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data) #endif }\n> \n> +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {\n> +\tu32 sr;\n> +\tu32 retry = 5;\n> +\n> +\tdo {\n> +\t\tsr = qspi_read32(priv->flags, &priv->regs->sr);\n> +\t\tif ((sr & QSPI_SR_BUSY_MASK) ||\n> +\t\t (sr & QSPI_SR_AHB_ACC_MASK) ||\n> +\t\t (sr & QSPI_SR_IP_ACC_MASK)) {\n> +\t\t\tdebug(\"The controller is busy, sr = 0x%x\\n\", sr);\n> +\t\t\tudelay(1);\n> +\t\t} else {\n> +\t\t\tbreak;\n> +\t\t}\n> +\t} while (--retry);\n> +\n> +\treturn (sr & QSPI_SR_BUSY_MASK) ||\n> +\t\t(sr & QSPI_SR_AHB_ACC_MASK) || (sr &\n> QSPI_SR_IP_ACC_MASK); }\n> +\n> static void qspi_set_lut(struct fsl_qspi_priv *priv) {\n> \tstruct fsl_qspi_regs *regs = priv->regs; @@ -765,6 +786,11 @@ int\n> qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,\n> \n> \tWATCHDOG_RESET();\n> \n> +\tif (qspi_controller_busy(priv)) {\n> +\t\tprintf(\"ERROR : The controller is busy\\n\");\n> +\t\treturn -EBUSY;\n> +\t}\n> +\n> \tif (dout) {\n> \t\tif (flags & SPI_XFER_BEGIN) {\n> \t\t\tpriv->cur_seqid = *(u8 *)dout;\n> diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h index 6cb3610..e468eb2\n> 100644\n> --- a/drivers/spi/fsl_qspi.h\n> +++ b/drivers/spi/fsl_qspi.h\n> @@ -105,6 +105,10 @@ struct fsl_qspi_regs {\n> #define QSPI_RBCT_RXBRD_SHIFT\t\t8\n> #define QSPI_RBCT_RXBRD_USEIPS\t\t(1 <<\n> QSPI_RBCT_RXBRD_SHIFT)\n> \n> +#define QSPI_SR_AHB_ACC_SHIFT\t\t2\n> +#define QSPI_SR_AHB_ACC_MASK\t\t(1 <<\n> QSPI_SR_AHB_ACC_SHIFT)\n> +#define QSPI_SR_IP_ACC_SHIFT\t\t1\n> +#define QSPI_SR_IP_ACC_MASK\t\t(1 << QSPI_SR_IP_ACC_SHIFT)\n> #define QSPI_SR_BUSY_SHIFT\t\t0\n> #define QSPI_SR_BUSY_MASK\t\t(1 << QSPI_SR_BUSY_SHIFT)\n> \n> --\n> 1.9.3","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1752919,"web_url":"http://patchwork.ozlabs.org/comment/1752919/","msgid":"","list_archive_url":null,"date":"2017-08-21T14:23:16","subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","submitter":{"id":20045,"url":"http://patchwork.ozlabs.org/api/people/20045/","name":"Jagan Teki","email":"jagannadh.teki@gmail.com"},"content":"On Mon, Aug 21, 2017 at 3:56 PM, Suresh Gupta wrote:\n> It is recommended to check either controller is free to take\n> new spi action. The IP_ACC and AHB_ACC bits indicates that\n> the controller is busy in IP or AHB mode respectively.\n> And the BUSY bit indicates that the controller is currently\n> busy handling a transaction to an external flash device\n>\n> Signed-off-by: Suresh Gupta \n> ---\n> drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++\n> drivers/spi/fsl_qspi.h | 4 ++++\n> 2 files changed, 30 insertions(+)\n>\n> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c\n> index 1dfa89a..69e9712 100644\n> --- a/drivers/spi/fsl_qspi.c\n> +++ b/drivers/spi/fsl_qspi.c\n> @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)\n> #endif\n> }\n>\n> +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv)\n> +{\n> + u32 sr;\n> + u32 retry = 5;\n> +\n> + do {\n> + sr = qspi_read32(priv->flags, &priv->regs->sr);\n> + if ((sr & QSPI_SR_BUSY_MASK) ||\n\nDoes this bit need? we can check the busy-state with AHB_ACC and IP_ACC\n\n> + (sr & QSPI_SR_AHB_ACC_MASK) ||\n> + (sr & QSPI_SR_IP_ACC_MASK)) {\n> + debug(\"The controller is busy, sr = 0x%x\\n\", sr);\n> + udelay(1);\n> + } else {\n> + break;\n> + }\n> + } while (--retry);\n\nThese retry and infine loop doesn't seems OK, how about using wait_for_bit?\n\n> +\n> + return (sr & QSPI_SR_BUSY_MASK) ||\n> + (sr & QSPI_SR_AHB_ACC_MASK) || (sr & QSPI_SR_IP_ACC_MASK);\n\nI didn't understand why these bits need to return? and when will the\nLUT trigger?\n\nthanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BLysuykt\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xbbX53mTFz9s7C\n\tfor ;\n\tTue, 22 Aug 2017 00:23:32 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid C9A91C21E0F; Mon, 21 Aug 2017 14:23:22 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 697B4C21D04;\n\tMon, 21 Aug 2017 14:23:20 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid A7A74C21D04; Mon, 21 Aug 2017 14:23:18 +0000 (UTC)","from mail-lf0-f67.google.com (mail-lf0-f67.google.com\n\t[209.85.215.67])\n\tby lists.denx.de (Postfix) with ESMTPS id 124A4C21C4E\n\tfor ; Mon, 21 Aug 2017 14:23:18 +0000 (UTC)","by mail-lf0-f67.google.com with SMTP id z12so2343119lfd.4\n\tfor ; Mon, 21 Aug 2017 07:23:18 -0700 (PDT)","by 10.25.143.131 with HTTP; Mon, 21 Aug 2017 07:23:16 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=SMxdJKYxe8fnaoSEAPpORA8Dn8XAbL2OtjAPhzb6ba4=;\n\tb=BLysuyktI3VSWqfZorWkxBQTmmiUXImcJ/SVXn8CdkY+sW2auTpltMLRMjX2b4AHOO\n\tImeAOxS+VvxplAnkjSl8TyObebaolp53Ajbqe0KdPN8kQjlKtP5ZJavATC6n3pTMS141\n\tsVQUgQeS2gGTbHWSV/oOL/QcKdQjtD1zspocaSIkrBVc3AEgxutD3Oz7JPLJuwxV+kDx\n\t178flgukcaX2Yp7EJ2y0ZOp5cvRfc2vMAWAz4CwKcVSZph9BR11EW/YRrvrq/Yu+Hk4N\n\tUZmCFBFo8yfvAsO9EwedIxpq50iQL/C0Xb31fkYtIldCtweQxFs9gLa7cbv3FLHeBYQt\n\tBJ7A==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=SMxdJKYxe8fnaoSEAPpORA8Dn8XAbL2OtjAPhzb6ba4=;\n\tb=UN0qWXASrgATuwWtIw/H0MZ42vZ75U5H1CYoib2BF+8/fQu/Qj5COfz1Yd7f6F96SH\n\t88ip7jDVGwjQx+0hggNVepCLb7BYhKrVsyhB89jwW/J39FfDl08YCRSRvs9BkVMUbvV5\n\tIACUH9txfpzdvTtl+TziExGqURxEWBH9u5qIckFg/wnNwu1/wAgcPXlEJV8CuWcLDgFv\n\t00a1o/QsV3EsEYNJh1FdxwoPMyogjAV5B6p/tnIY9Bn9Jb+GqWTBW1BCJ5M9pBSuGv6f\n\tiQPSHncWqP2YPdap//oaJMjz7N6T7yyk7JRoq8dD3DNypdWFdyeFtTZ2v9fwzhJ2n9Ww\n\taaOA==","X-Gm-Message-State":"AHYfb5g4Sfq+fYot0hfH1JsUYNGDapOVjN88Zk4kf/vr+O53s4NenOh+\n\tCBbIs7XtSWK14nUhD70uXDIveheXIw==","X-Received":"by 10.25.80.13 with SMTP id e13mr5397952lfb.92.1503325397391;\n\tMon, 21 Aug 2017 07:23:17 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1503311174-3574-1-git-send-email-suresh.gupta@nxp.com>","References":"<1503311174-3574-1-git-send-email-suresh.gupta@nxp.com>","From":"Jagan Teki ","Date":"Mon, 21 Aug 2017 19:53:16 +0530","Message-ID":"","To":"Suresh Gupta ","Cc":"\"u-boot@lists.denx.de\" ,\n\tJagan Teki ","Subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1753018,"web_url":"http://patchwork.ozlabs.org/comment/1753018/","msgid":"","list_archive_url":null,"date":"2017-08-21T16:03:50","subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","submitter":{"id":67822,"url":"http://patchwork.ozlabs.org/api/people/67822/","name":"York Sun","email":"york.sun@nxp.com"},"content":"I shouldn't take this patch without Jagan's ack.\n\nYork\n\nOn 08/21/2017 05:03 AM, Suresh Gupta wrote:\n> Hi York,\n> \n> Can I delegate this patch to you? Delegate to Jagan (SPI Maintainer) delays the acceptance process.\n> \n> Thanks\n> SuresH\n> \n>> -----Original Message-----\n>> From: Suresh Gupta [mailto:suresh.gupta@nxp.com]\n>> Sent: Monday, August 21, 2017 3:56 PM\n>> To: u-boot@lists.denx.de\n>> Cc: York Sun ; jagan@openedev.com; Prabhakar Kushwaha\n>> ; Suresh Gupta \n>> Subject: [PATCH] spi: fsl_qspi: Add controller busy check before new spi\n>> operation\n>>\n>> It is recommended to check either controller is free to take new spi action. The\n>> IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode\n>> respectively.\n>> And the BUSY bit indicates that the controller is currently busy handling a\n>> transaction to an external flash device\n>>\n>> Signed-off-by: Suresh Gupta \n>> ---\n>> drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++ drivers/spi/fsl_qspi.h\n>> | 4 ++++\n>> 2 files changed, 30 insertions(+)\n>>\n>> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 1dfa89a..69e9712\n>> 100644\n>> --- a/drivers/spi/fsl_qspi.c\n>> +++ b/drivers/spi/fsl_qspi.c\n>> @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data) #endif }\n>>\n>> +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {\n>> +\tu32 sr;\n>> +\tu32 retry = 5;\n>> +\n>> +\tdo {\n>> +\t\tsr = qspi_read32(priv->flags, &priv->regs->sr);\n>> +\t\tif ((sr & QSPI_SR_BUSY_MASK) ||\n>> +\t\t (sr & QSPI_SR_AHB_ACC_MASK) ||\n>> +\t\t (sr & QSPI_SR_IP_ACC_MASK)) {\n>> +\t\t\tdebug(\"The controller is busy, sr = 0x%x\\n\", sr);\n>> +\t\t\tudelay(1);\n>> +\t\t} else {\n>> +\t\t\tbreak;\n>> +\t\t}\n>> +\t} while (--retry);\n>> +\n>> +\treturn (sr & QSPI_SR_BUSY_MASK) ||\n>> +\t\t(sr & QSPI_SR_AHB_ACC_MASK) || (sr &\n>> QSPI_SR_IP_ACC_MASK); }\n>> +\n>> static void qspi_set_lut(struct fsl_qspi_priv *priv) {\n>> \tstruct fsl_qspi_regs *regs = priv->regs; @@ -765,6 +786,11 @@ int\n>> qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,\n>>\n>> \tWATCHDOG_RESET();\n>>\n>> +\tif (qspi_controller_busy(priv)) {\n>> +\t\tprintf(\"ERROR : The controller is busy\\n\");\n>> +\t\treturn -EBUSY;\n>> +\t}\n>> +\n>> \tif (dout) {\n>> \t\tif (flags & SPI_XFER_BEGIN) {\n>> \t\t\tpriv->cur_seqid = *(u8 *)dout;\n>> diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h index 6cb3610..e468eb2\n>> 100644\n>> --- a/drivers/spi/fsl_qspi.h\n>> +++ b/drivers/spi/fsl_qspi.h\n>> @@ -105,6 +105,10 @@ struct fsl_qspi_regs {\n>> #define QSPI_RBCT_RXBRD_SHIFT\t\t8\n>> #define QSPI_RBCT_RXBRD_USEIPS\t\t(1 <<\n>> QSPI_RBCT_RXBRD_SHIFT)\n>>\n>> +#define QSPI_SR_AHB_ACC_SHIFT\t\t2\n>> +#define QSPI_SR_AHB_ACC_MASK\t\t(1 <<\n>> QSPI_SR_AHB_ACC_SHIFT)\n>> +#define QSPI_SR_IP_ACC_SHIFT\t\t1\n>> +#define QSPI_SR_IP_ACC_MASK\t\t(1 << QSPI_SR_IP_ACC_SHIFT)\n>> #define QSPI_SR_BUSY_SHIFT\t\t0\n>> #define QSPI_SR_BUSY_MASK\t\t(1 << QSPI_SR_BUSY_SHIFT)\n>>\n>> --\n>> 1.9.3\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1753736,"web_url":"http://patchwork.ozlabs.org/comment/1753736/","msgid":"","list_archive_url":null,"date":"2017-08-22T10:49:16","subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","submitter":{"id":70239,"url":"http://patchwork.ozlabs.org/api/people/70239/","name":"Suresh Gupta","email":"suresh.gupta@nxp.com"},"content":"Thanks Jagan for reviewing the code. \r\nPlease find comments in line \r\n\r\n> -----Original Message-----\r\n> From: Jagan Teki [mailto:jagannadh.teki@gmail.com]\r\n> Sent: Monday, August 21, 2017 7:53 PM\r\n> To: Suresh Gupta \r\n> Cc: u-boot@lists.denx.de; Jagan Teki \r\n> Subject: Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before\r\n> new spi operation\r\n> \r\n> On Mon, Aug 21, 2017 at 3:56 PM, Suresh Gupta \r\n> wrote:\r\n> > It is recommended to check either controller is free to take new spi\r\n> > action. The IP_ACC and AHB_ACC bits indicates that the controller is\r\n> > busy in IP or AHB mode respectively.\r\n> > And the BUSY bit indicates that the controller is currently busy\r\n> > handling a transaction to an external flash device\r\n> >\r\n> > Signed-off-by: Suresh Gupta \r\n> > ---\r\n> > drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++\r\n> > drivers/spi/fsl_qspi.h | 4 ++++\r\n> > 2 files changed, 30 insertions(+)\r\n> >\r\n> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index\r\n> > 1dfa89a..69e9712 100644\r\n> > --- a/drivers/spi/fsl_qspi.c\r\n> > +++ b/drivers/spi/fsl_qspi.c\r\n> > @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)\r\n> > #endif }\r\n> >\r\n> > +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {\r\n> > + u32 sr;\r\n> > + u32 retry = 5;\r\n> > +\r\n> > + do {\r\n> > + sr = qspi_read32(priv->flags, &priv->regs->sr);\r\n> > + if ((sr & QSPI_SR_BUSY_MASK) ||\r\n> \r\n> Does this bit need? we can check the busy-state with AHB_ACC and IP_ACC\r\n\r\nThe definition of the three bits is \r\nBit2 - AHB_ACC: AHB Access: Asserted when the transaction currently executed was initiated by AHB bus.\r\nBit1 - IP_ACC: IP Access: Asserted when transaction currently executed was initiated by IP bus.\r\nBit0 - BUSY: Module Busy: Asserted when module is currently busy handling a transaction to an external flash device.\r\n\r\nAlso, the below are statements mentioned in the IP Block Guide\r\nFor AHB Access: Since the read access is triggered via the AHB bus, the QSPI_SR[AHB_ACC] \r\n\t\tstatus bit is set driving in turn the QSPI_SR[BUSY] bit until the transaction is finished.\r\nFor IP Access: Since the read access is triggered by an IP command the IP_ACC status bit and\r\n\t\tthe BUSY bit are both set (both are located in the Status Register (QSPI_SR) ).\r\n\r\nSo, BUSY flag is set when the controller is busy in communication with FLASH and this is true for both IP and AHB mode.\r\nThat’s the reason checking all three status bits ensures us that controller is free. \r\n\r\n> \r\n> > + (sr & QSPI_SR_AHB_ACC_MASK) ||\r\n> > + (sr & QSPI_SR_IP_ACC_MASK)) {\r\n> > + debug(\"The controller is busy, sr = 0x%x\\n\", sr);\r\n> > + udelay(1);\r\n> > + } else {\r\n> > + break;\r\n> > + }\r\n> > + } while (--retry);\r\n> \r\n> These retry and infine loop doesn't seems OK, how about using wait_for_bit?\r\nOk, I will use below and send a new patch\r\n\r\nret = wait_for_bit(__func__, regs->sr,\r\n QSPI_SR_BUSY_MASK |\r\n QSPI_SR_AHB_ACC_MASK |\r\n QSPI_SR_IP_ACC_MASK,\r\n false, 1000, false);\r\n> \r\n> > +\r\n> > + return (sr & QSPI_SR_BUSY_MASK) ||\r\n> > + (sr & QSPI_SR_AHB_ACC_MASK) || (sr &\r\n> > + QSPI_SR_IP_ACC_MASK);\r\n> \r\n> I didn't understand why these bits need to return? \r\nAfter wait_for_bit, this is not required \r\n\r\n> and when will the LUT trigger?\r\nThe check is added as it is recommended that before any new transaction, these bits should be 0 i.e. controller is not busy.\r\nThis check is required before all new types of transaction with FLASH. \r\nSo I added this in qspi_xfer() which intern calls actual hardware operations like qspi_op_write, qspi_op_erase, qspi_ahb_read, qspi_op_rdsr etc., which triggers the LUT. \r\n\r\n> \r\n> thanks!\r\n> --\r\n> Jagan Teki\r\n> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream\r\n> Maintainer Hyderabad, India.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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A:1; MX:1; LANG:en; ","received-spf":"None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)","spamdiagnosticoutput":"1:99","spamdiagnosticmetadata":"NSPM","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-originalarrivaltime":"22 Aug 2017 10:49:16.3650\n\t(UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DB5PR04MB1447","Cc":"\"u-boot@lists.denx.de\" ,\n\tJagan Teki ","Subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1754189,"web_url":"http://patchwork.ozlabs.org/comment/1754189/","msgid":"","list_archive_url":null,"date":"2017-08-22T16:25:31","subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","submitter":{"id":67822,"url":"http://patchwork.ozlabs.org/api/people/67822/","name":"York Sun","email":"york.sun@nxp.com"},"content":"On 08/21/2017 03:25 AM, Suresh Gupta wrote:\n> It is recommended to check either controller is free to take\n> new spi action. The IP_ACC and AHB_ACC bits indicates that\n> the controller is busy in IP or AHB mode respectively.\n> And the BUSY bit indicates that the controller is currently\n> busy handling a transaction to an external flash device\n> \n> Signed-off-by: Suresh Gupta \n> ---\n> drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++\n> drivers/spi/fsl_qspi.h | 4 ++++\n> 2 files changed, 30 insertions(+)\n> \n> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c\n> index 1dfa89a..69e9712 100644\n> --- a/drivers/spi/fsl_qspi.c\n> +++ b/drivers/spi/fsl_qspi.c\n> @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)\n> #endif\n> }\n> \n> +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv)\n> +{\n> +\tu32 sr;\n> +\tu32 retry = 5;\n> +\n> +\tdo {\n> +\t\tsr = qspi_read32(priv->flags, &priv->regs->sr);\n> +\t\tif ((sr & QSPI_SR_BUSY_MASK) ||\n> +\t\t (sr & QSPI_SR_AHB_ACC_MASK) ||\n> +\t\t (sr & QSPI_SR_IP_ACC_MASK)) {\n> +\t\t\tdebug(\"The controller is busy, sr = 0x%x\\n\", sr);\n> +\t\t\tudelay(1);\n> +\t\t} else {\n> +\t\t\tbreak;\n> +\t\t}\n> +\t} while (--retry);\n\nDoes the 5 microsecond-delay make any difference?\n\n> +\n> +\treturn (sr & QSPI_SR_BUSY_MASK) ||\n> +\t\t(sr & QSPI_SR_AHB_ACC_MASK) || (sr & QSPI_SR_IP_ACC_MASK);\n> +}\n> +\n> static void qspi_set_lut(struct fsl_qspi_priv *priv)\n> {\n> \tstruct fsl_qspi_regs *regs = priv->regs;\n> @@ -765,6 +786,11 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,\n> \n> \tWATCHDOG_RESET();\n> \n> +\tif (qspi_controller_busy(priv)) {\n> +\t\tprintf(\"ERROR : The controller is busy\\n\");\n> +\t\treturn -EBUSY;\n> +\t}\n\nIf the controller should never be busy for this operation, I wonder if \nyou really need a delay above.\n\nYork","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1754650,"web_url":"http://patchwork.ozlabs.org/comment/1754650/","msgid":"","list_archive_url":null,"date":"2017-08-23T03:51:09","subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","submitter":{"id":70239,"url":"http://patchwork.ozlabs.org/api/people/70239/","name":"Suresh Gupta","email":"suresh.gupta@nxp.com"},"content":"> -----Original Message-----\n> From: York Sun\n> Sent: Tuesday, August 22, 2017 9:56 PM\n> To: Suresh Gupta ; u-boot@lists.denx.de\n> Cc: jagan@openedev.com; Prabhakar Kushwaha\n> \n> Subject: Re: [PATCH] spi: fsl_qspi: Add controller busy check before new spi\n> operation\n> \n> On 08/21/2017 03:25 AM, Suresh Gupta wrote:\n> > It is recommended to check either controller is free to take new spi\n> > action. The IP_ACC and AHB_ACC bits indicates that the controller is\n> > busy in IP or AHB mode respectively.\n> > And the BUSY bit indicates that the controller is currently busy\n> > handling a transaction to an external flash device\n> >\n> > Signed-off-by: Suresh Gupta \n> > ---\n> > drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++\n> > drivers/spi/fsl_qspi.h | 4 ++++\n> > 2 files changed, 30 insertions(+)\n> >\n> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index\n> > 1dfa89a..69e9712 100644\n> > --- a/drivers/spi/fsl_qspi.c\n> > +++ b/drivers/spi/fsl_qspi.c\n> > @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)\n> > #endif\n> > }\n> >\n> > +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {\n> > +\tu32 sr;\n> > +\tu32 retry = 5;\n> > +\n> > +\tdo {\n> > +\t\tsr = qspi_read32(priv->flags, &priv->regs->sr);\n> > +\t\tif ((sr & QSPI_SR_BUSY_MASK) ||\n> > +\t\t (sr & QSPI_SR_AHB_ACC_MASK) ||\n> > +\t\t (sr & QSPI_SR_IP_ACC_MASK)) {\n> > +\t\t\tdebug(\"The controller is busy, sr = 0x%x\\n\", sr);\n> > +\t\t\tudelay(1);\n> > +\t\t} else {\n> > +\t\t\tbreak;\n> > +\t\t}\n> > +\t} while (--retry);\n> \n> Does the 5 microsecond-delay make any difference?\n> \n> > +\n> > +\treturn (sr & QSPI_SR_BUSY_MASK) ||\n> > +\t\t(sr & QSPI_SR_AHB_ACC_MASK) || (sr &\n> QSPI_SR_IP_ACC_MASK); }\n> > +\n> > static void qspi_set_lut(struct fsl_qspi_priv *priv)\n> > {\n> > \tstruct fsl_qspi_regs *regs = priv->regs; @@ -765,6 +786,11 @@ int\n> > qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,\n> >\n> > \tWATCHDOG_RESET();\n> >\n> > +\tif (qspi_controller_busy(priv)) {\n> > +\t\tprintf(\"ERROR : The controller is busy\\n\");\n> > +\t\treturn -EBUSY;\n> > +\t}\n> \n> If the controller should never be busy for this operation, I wonder if you really\n> need a delay above.\n\nAs we see in our setup that controller get free after some time. So, I took 5 microseconds as arbitrary number. \nMoreover, below statement [1] of BG points that controller gets free after prefetch completes. \n\n[1] Snapshot from RM: \nFor any AHB access, the sequence pointed to by the QSPI_BFGENCR [SEQID] field is used for\nthe flash transaction initiated. The data is returned to the master as soon as the requested\namount is read from the serial flash. The controller however, continues to prefetch the\nrest of the data in anticipation of a next consecutive request.\n \n> \n> York","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"n+lnsfkO\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=suresh.gupta@nxp.com; "],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xcYPn4S5dz9sCZ\n\tfor ;\n\tWed, 23 Aug 2017 13:51:24 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 0761DC21E41; Wed, 23 Aug 2017 03:51:15 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id D025CC21DCE;\n\tWed, 23 Aug 2017 03:51:12 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 32BC9C21DCE; Wed, 23 Aug 2017 03:51:12 +0000 (UTC)","from EUR03-DB5-obe.outbound.protection.outlook.com\n\t(mail-eopbgr40079.outbound.protection.outlook.com [40.107.4.79])\n\tby lists.denx.de (Postfix) with ESMTPS id 9596CC21C40\n\tfor ; Wed, 23 Aug 2017 03:51:11 +0000 (UTC)","from DB5PR04MB1350.eurprd04.prod.outlook.com (10.162.220.156) by\n\tDB5PR04MB1206.eurprd04.prod.outlook.com (10.162.155.24) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.1.1362.18; Wed, 23 Aug 2017 03:51:10 +0000","from DB5PR04MB1350.eurprd04.prod.outlook.com\n\t([fe80::7175:9fbf:f392:a88f]) by\n\tDB5PR04MB1350.eurprd04.prod.outlook.com\n\t([fe80::7175:9fbf:f392:a88f%13]) with mapi id 15.01.1362.019;\n\tWed, 23 Aug 2017 03:51:09 +0000"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.6 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H2, RCVD_IN_SORBS_WEB, SPF_HELO_PASS,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=B9LfDPxdJq3dtxLe1gSBwJkelR4gUvuPRI9uwICP6EM=;\n\tb=n+lnsfkOKVaFfbHhkQk8IvjgobMvnU8rQtu13czWaQEhQA2QniNLokVjpirSVHVTjVOIZm23ZIAq4GN2Okf6O5zGK9AjPPX4kz2k661CeCNhs7SOnuIHRFYazVw8sanhLZmfCOgBfqxKYjksXvV3dvitqlm/N9fYFdyeLldKbC0=","From":"Suresh Gupta ","To":"York Sun ,\n\t\"u-boot@lists.denx.de\" ","Thread-Topic":"[PATCH] spi: fsl_qspi: Add controller busy check before new spi\n\toperation","Thread-Index":"AQHTGmfSy+b8JHZqmkue7oAhJMoHYqKRTjYg","Date":"Wed, 23 Aug 2017 03:51:09 +0000","Message-ID":"","References":"<1503311174-3574-1-git-send-email-suresh.gupta@nxp.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"n+lnsfkO\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=suresh.gupta@nxp.com; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1754688,"web_url":"http://patchwork.ozlabs.org/comment/1754688/","msgid":"","list_archive_url":null,"date":"2017-08-23T05:27:25","subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","submitter":{"id":20045,"url":"http://patchwork.ozlabs.org/api/people/20045/","name":"Jagan Teki","email":"jagannadh.teki@gmail.com"},"content":"On Tue, Aug 22, 2017 at 4:19 PM, Suresh Gupta wrote:\n> Thanks Jagan for reviewing the code.\n> Please find comments in line\n>\n>> -----Original Message-----\n>> From: Jagan Teki [mailto:jagannadh.teki@gmail.com]\n>> Sent: Monday, August 21, 2017 7:53 PM\n>> To: Suresh Gupta \n>> Cc: u-boot@lists.denx.de; Jagan Teki \n>> Subject: Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before\n>> new spi operation\n>>\n>> On Mon, Aug 21, 2017 at 3:56 PM, Suresh Gupta \n>> wrote:\n>> > It is recommended to check either controller is free to take new spi\n>> > action. The IP_ACC and AHB_ACC bits indicates that the controller is\n>> > busy in IP or AHB mode respectively.\n>> > And the BUSY bit indicates that the controller is currently busy\n>> > handling a transaction to an external flash device\n>> >\n>> > Signed-off-by: Suresh Gupta \n>> > ---\n>> > drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++\n>> > drivers/spi/fsl_qspi.h | 4 ++++\n>> > 2 files changed, 30 insertions(+)\n>> >\n>> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index\n>> > 1dfa89a..69e9712 100644\n>> > --- a/drivers/spi/fsl_qspi.c\n>> > +++ b/drivers/spi/fsl_qspi.c\n>> > @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)\n>> > #endif }\n>> >\n>> > +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {\n>> > + u32 sr;\n>> > + u32 retry = 5;\n>> > +\n>> > + do {\n>> > + sr = qspi_read32(priv->flags, &priv->regs->sr);\n>> > + if ((sr & QSPI_SR_BUSY_MASK) ||\n>>\n>> Does this bit need? we can check the busy-state with AHB_ACC and IP_ACC\n>\n> The definition of the three bits is\n> Bit2 - AHB_ACC: AHB Access: Asserted when the transaction currently executed was initiated by AHB bus.\n> Bit1 - IP_ACC: IP Access: Asserted when transaction currently executed was initiated by IP bus.\n> Bit0 - BUSY: Module Busy: Asserted when module is currently busy handling a transaction to an external flash device.\n>\n> Also, the below are statements mentioned in the IP Block Guide\n> For AHB Access: Since the read access is triggered via the AHB bus, the QSPI_SR[AHB_ACC]\n> status bit is set driving in turn the QSPI_SR[BUSY] bit until the transaction is finished.\n> For IP Access: Since the read access is triggered by an IP command the IP_ACC status bit and\n> the BUSY bit are both set (both are located in the Status Register (QSPI_SR) ).\n>\n> So, BUSY flag is set when the controller is busy in communication with FLASH and this is true for both IP and AHB mode.\n> That’s the reason checking all three status bits ensures us that controller is free.\n>\n>>\n>> > + (sr & QSPI_SR_AHB_ACC_MASK) ||\n>> > + (sr & QSPI_SR_IP_ACC_MASK)) {\n>> > + debug(\"The controller is busy, sr = 0x%x\\n\", sr);\n>> > + udelay(1);\n>> > + } else {\n>> > + break;\n>> > + }\n>> > + } while (--retry);\n>>\n>> These retry and infine loop doesn't seems OK, how about using wait_for_bit?\n> Ok, I will use below and send a new patch\n>\n> ret = wait_for_bit(__func__, regs->sr,\n> QSPI_SR_BUSY_MASK |\n> QSPI_SR_AHB_ACC_MASK |\n> QSPI_SR_IP_ACC_MASK,\n> false, 1000, false);\n>>\n>> > +\n>> > + return (sr & QSPI_SR_BUSY_MASK) ||\n>> > + (sr & QSPI_SR_AHB_ACC_MASK) || (sr &\n>> > + QSPI_SR_IP_ACC_MASK);\n>>\n>> I didn't understand why these bits need to return?\n> After wait_for_bit, this is not required\n>\n>> and when will the LUT trigger?\n> The check is added as it is recommended that before any new transaction, these bits should be 0 i.e. controller is not busy.\n> This check is required before all new types of transaction with FLASH.\n> So I added this in qspi_xfer() which intern calls actual hardware operations like qspi_op_write, qspi_op_erase, qspi_ahb_read, qspi_op_rdsr etc., which triggers the LUT.\n\nWhat about moving this in claim_bus?, because xfer will call each\ntransfer with each transaction.and of course while probe or each\noperation claim_bus is initiating.\n\nthanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1754738,"web_url":"http://patchwork.ozlabs.org/comment/1754738/","msgid":"","list_archive_url":null,"date":"2017-08-23T06:21:16","subject":"Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check\n\tbefore new spi operation","submitter":{"id":70239,"url":"http://patchwork.ozlabs.org/api/people/70239/","name":"Suresh Gupta","email":"suresh.gupta@nxp.com"},"content":"> -----Original Message-----\r\n> From: Jagan Teki [mailto:jagannadh.teki@gmail.com]\r\n> Sent: Wednesday, August 23, 2017 10:57 AM\r\n> To: Suresh Gupta \r\n> Cc: u-boot@lists.denx.de; Jagan Teki \r\n> Subject: Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before\r\n> new spi operation\r\n> \r\n> On Tue, Aug 22, 2017 at 4:19 PM, Suresh Gupta \r\n> wrote:\r\n> > Thanks Jagan for reviewing the code.\r\n> > Please find comments in line\r\n> >\r\n> >> -----Original Message-----\r\n> >> From: Jagan Teki [mailto:jagannadh.teki@gmail.com]\r\n> >> Sent: Monday, August 21, 2017 7:53 PM\r\n> >> To: Suresh Gupta \r\n> >> Cc: u-boot@lists.denx.de; Jagan Teki \r\n> >> Subject: Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy\r\n> >> check before new spi operation\r\n> >>\r\n> >> On Mon, Aug 21, 2017 at 3:56 PM, Suresh Gupta \r\n> >> wrote:\r\n> >> > It is recommended to check either controller is free to take new\r\n> >> > spi action. The IP_ACC and AHB_ACC bits indicates that the\r\n> >> > controller is busy in IP or AHB mode respectively.\r\n> >> > And the BUSY bit indicates that the controller is currently busy\r\n> >> > handling a transaction to an external flash device\r\n> >> >\r\n> >> > Signed-off-by: Suresh Gupta \r\n> >> > ---\r\n> >> > drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++\r\n> >> > drivers/spi/fsl_qspi.h | 4 ++++\r\n> >> > 2 files changed, 30 insertions(+)\r\n> >> >\r\n> >> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index\r\n> >> > 1dfa89a..69e9712 100644\r\n> >> > --- a/drivers/spi/fsl_qspi.c\r\n> >> > +++ b/drivers/spi/fsl_qspi.c\r\n> >> > @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)\r\n> >> > #endif }\r\n> >> >\r\n> >> > +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {\r\n> >> > + u32 sr;\r\n> >> > + u32 retry = 5;\r\n> >> > +\r\n> >> > + do {\r\n> >> > + sr = qspi_read32(priv->flags, &priv->regs->sr);\r\n> >> > + if ((sr & QSPI_SR_BUSY_MASK) ||\r\n> >>\r\n> >> Does this bit need? we can check the busy-state with AHB_ACC and\r\n> >> IP_ACC\r\n> >\r\n> > The definition of the three bits is\r\n> > Bit2 - AHB_ACC: AHB Access: Asserted when the transaction currently\r\n> executed was initiated by AHB bus.\r\n> > Bit1 - IP_ACC: IP Access: Asserted when transaction currently executed was\r\n> initiated by IP bus.\r\n> > Bit0 - BUSY: Module Busy: Asserted when module is currently busy handling a\r\n> transaction to an external flash device.\r\n> >\r\n> > Also, the below are statements mentioned in the IP Block Guide For AHB\r\n> > Access: Since the read access is triggered via the AHB bus, the\r\n> QSPI_SR[AHB_ACC]\r\n> > status bit is set driving in turn the QSPI_SR[BUSY] bit until the\r\n> transaction is finished.\r\n> > For IP Access: Since the read access is triggered by an IP command the IP_ACC\r\n> status bit and\r\n> > the BUSY bit are both set (both are located in the Status Register\r\n> (QSPI_SR) ).\r\n> >\r\n> > So, BUSY flag is set when the controller is busy in communication with FLASH\r\n> and this is true for both IP and AHB mode.\r\n> > That’s the reason checking all three status bits ensures us that controller is\r\n> free.\r\n> >\r\n> >>\r\n> >> > + (sr & QSPI_SR_AHB_ACC_MASK) ||\r\n> >> > + (sr & QSPI_SR_IP_ACC_MASK)) {\r\n> >> > + debug(\"The controller is busy, sr = 0x%x\\n\", sr);\r\n> >> > + udelay(1);\r\n> >> > + } else {\r\n> >> > + break;\r\n> >> > + }\r\n> >> > + } while (--retry);\r\n> >>\r\n> >> These retry and infine loop doesn't seems OK, how about using wait_for_bit?\r\n> > Ok, I will use below and send a new patch\r\n> >\r\n> > ret = wait_for_bit(__func__, regs->sr,\r\n> > QSPI_SR_BUSY_MASK |\r\n> > QSPI_SR_AHB_ACC_MASK |\r\n> > QSPI_SR_IP_ACC_MASK,\r\n> > false, 1000, false);\r\n> >>\r\n> >> > +\r\n> >> > + return (sr & QSPI_SR_BUSY_MASK) ||\r\n> >> > + (sr & QSPI_SR_AHB_ACC_MASK) || (sr &\r\n> >> > + QSPI_SR_IP_ACC_MASK);\r\n> >>\r\n> >> I didn't understand why these bits need to return?\r\n> > After wait_for_bit, this is not required\r\n> >\r\n> >> and when will the LUT trigger?\r\n> > The check is added as it is recommended that before any new transaction,\r\n> these bits should be 0 i.e. controller is not busy.\r\n> > This check is required before all new types of transaction with FLASH.\r\n> > So I added this in qspi_xfer() which intern calls actual hardware operations like\r\n> qspi_op_write, qspi_op_erase, qspi_ahb_read, qspi_op_rdsr etc., which triggers\r\n> the LUT.\r\n> \r\n> What about moving this in claim_bus?, because xfer will call each transfer with\r\n> each transaction.and of course while probe or each operation claim_bus is\r\n> initiating.\r\n> \r\nI will check and let you know tomorrow. \r\n\r\n\r\n> thanks!\r\n> --\r\n> Jagan Teki\r\n> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream\r\n> Maintainer Hyderabad, India.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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