[{"id":1758026,"web_url":"http://patchwork.ozlabs.org/comment/1758026/","msgid":"","list_archive_url":null,"date":"2017-08-26T13:39:10","subject":"Re: [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"On 15 August 2017 at 23:41, Bin Meng wrote:\n> This adds initial Intel Braswell SoC support. It uses Intel FSP\n> to initialize the chipset.\n>\n> Similar to its predecessor BayTrail, there are some work to do to\n> enable the legacy UART integrated in the Braswell SoC.\n>\n> Signed-off-by: Bin Meng \n> ---\n>\n> arch/x86/Kconfig | 1 +\n> arch/x86/cpu/Makefile | 1 +\n> arch/x86/cpu/braswell/Kconfig | 38 +++++++\n> arch/x86/cpu/braswell/Makefile | 7 ++\n> arch/x86/cpu/braswell/braswell.c | 36 ++++++\n> arch/x86/cpu/braswell/cpu.c | 170 +++++++++++++++++++++++++++++\n> arch/x86/cpu/braswell/early_uart.c | 86 +++++++++++++++\n> arch/x86/include/asm/arch-braswell/iomap.h | 50 +++++++++\n> 8 files changed, 389 insertions(+)\n> create mode 100644 arch/x86/cpu/braswell/Kconfig\n> create mode 100644 arch/x86/cpu/braswell/Makefile\n> create mode 100644 arch/x86/cpu/braswell/braswell.c\n> create mode 100644 arch/x86/cpu/braswell/cpu.c\n> create mode 100644 arch/x86/cpu/braswell/early_uart.c\n> create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h\n\nReviewed-by: Simon Glass \n\nA few nits / suggestions below.\n\n>\n> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig\n> index f72d307..9620764 100644\n> --- a/arch/x86/Kconfig\n> +++ b/arch/x86/Kconfig\n> @@ -108,6 +108,7 @@ source \"board/intel/Kconfig\"\n>\n> # platform-specific options below\n> source \"arch/x86/cpu/baytrail/Kconfig\"\n> +source \"arch/x86/cpu/braswell/Kconfig\"\n> source \"arch/x86/cpu/broadwell/Kconfig\"\n> source \"arch/x86/cpu/coreboot/Kconfig\"\n> source \"arch/x86/cpu/ivybridge/Kconfig\"\n> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile\n> index 999429e..94cdff1 100644\n> --- a/arch/x86/cpu/Makefile\n> +++ b/arch/x86/cpu/Makefile\n> @@ -27,6 +27,7 @@ endif\n>\n> obj-y += intel_common/\n> obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/\n> +obj-$(CONFIG_INTEL_BRASWELL) += braswell/\n> obj-$(CONFIG_INTEL_BROADWELL) += broadwell/\n> obj-$(CONFIG_SYS_COREBOOT) += coreboot/\n> obj-$(CONFIG_EFI_APP) += efi/\n> diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig\n> new file mode 100644\n> index 0000000..c993889\n> --- /dev/null\n> +++ b/arch/x86/cpu/braswell/Kconfig\n> @@ -0,0 +1,38 @@\n> +#\n> +# Copyright (C) 2017, Bin Meng \n> +#\n> +# SPDX-License-Identifier: GPL-2.0+\n> +#\n> +\n> +config INTEL_BRASWELL\n> + bool\n> + select HAVE_FSP\n> + select ARCH_MISC_INIT\n> + imply HAVE_INTEL_ME\n> + imply HAVE_VBT\n> + imply ENABLE_MRC_CACHE\n> + imply ENV_IS_IN_SPI_FLASH\n> + imply AHCI_PCI\n> + imply ICH_SPI\n> + imply MMC\n> + imply MMC_PCI\n> + imply MMC_SDHCI\n> + imply MMC_SDHCI_SDMA\n> + imply SCSI\n> + imply SPI_FLASH\n> + imply SYS_NS16550\n> + imply USB\n> + imply USB_XHCI_HCD\n> + imply VIDEO_FSP\n> +\n> +if INTEL_BRASWELL\n> +\n> +config FSP_ADDR\n> + hex\n> + default 0xfff20000\n> +\n> +config FSP_LOCKDOWN_SPI\n> + bool\n> + default y\n> +\n> +endif\n> diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile\n> new file mode 100644\n> index 0000000..19bcee6\n> --- /dev/null\n> +++ b/arch/x86/cpu/braswell/Makefile\n> @@ -0,0 +1,7 @@\n> +#\n> +# Copyright (C) 2017, Bin Meng \n> +#\n> +# SPDX-License-Identifier: GPL-2.0+\n> +#\n> +\n> +obj-y += braswell.o cpu.o early_uart.o\n> diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c\n> new file mode 100644\n> index 0000000..37099aa\n> --- /dev/null\n> +++ b/arch/x86/cpu/braswell/braswell.c\n> @@ -0,0 +1,36 @@\n> +/*\n> + * Copyright (C) 2017, Bin Meng \n> + *\n> + * SPDX-License-Identifier: GPL-2.0+\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +int arch_cpu_init(void)\n> +{\n> + post_code(POST_CPU_INIT);\n> +\n> + return x86_cpu_init_f();\n> +}\n> +\n> +int arch_misc_init(void)\n> +{\n> +#ifdef CONFIG_ENABLE_MRC_CACHE\n> + /*\n> + * We intend not to check any return value here, as even MRC cache\n> + * is not saved successfully, it is not a severe error that will\n> + * prevent system from continuing to boot.\n> + */\n> + mrccache_save();\n> +#endif\n> +\n> + return 0;\n> +}\n> +\n> +void reset_cpu(ulong addr)\n> +{\n> + /* cold reset */\n> + x86_full_reset();\n> +}\n> diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c\n> new file mode 100644\n> index 0000000..6ff9036\n> --- /dev/null\n> +++ b/arch/x86/cpu/braswell/cpu.c\n> @@ -0,0 +1,170 @@\n> +/*\n> + * Copyright (C) 2017, Bin Meng \n> + *\n> + * SPDX-License-Identifier: GPL-2.0+\n> + *\n> + * Derived from arch/x86/cpu/baytrail/cpu.c\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +static const unsigned int braswell_bus_freq_table[] = {\n> + 83333333,\n> + 100000000,\n> + 133333333,\n> + 116666666,\n> + 80000000,\n> + 93333333,\n> + 90000000,\n> + 88900000,\n> + 87500000\n> +};\n> +\n> +static unsigned int braswell_bus_freq(void)\n> +{\n> + msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);\n> +\n> + if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))\n> + return braswell_bus_freq_table[clk_info.lo & 0xf];\n> +\n> + return 0;\n> +}\n> +\n> +static unsigned long braswell_tsc_freq(void)\n> +{\n> + msr_t platform_info;\n> + ulong bclk = braswell_bus_freq();\n> +\n> + if (!bclk)\n> + return 0;\n> +\n> + platform_info = msr_read(MSR_PLATFORM_INFO);\n> +\n> + return bclk * ((platform_info.lo >> 8) & 0xff);\n> +}\n> +\n> +static int braswell_get_info(struct udevice *dev, struct cpu_info *info)\n> +{\n> + info->cpu_freq = braswell_tsc_freq();\n> + info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);\n> +\n> + return 0;\n> +}\n> +\n> +static int braswell_get_count(struct udevice *dev)\n> +{\n> + int ecx = 0;\n> +\n> + /*\n> + * Use the algorithm described in Intel 64 and IA-32 Architectures\n> + * Software Developer's Manual Volume 3 (3A, 3B & 3C): System\n> + * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping\n> + * of CPUID Extended Topology Leaf.\n> + */\n> + while (1) {\n> + struct cpuid_result leaf_b;\n> +\n> + leaf_b = cpuid_ext(0xb, ecx);\n> +\n> + /*\n> + * Braswell doesn't have hyperthreading so just determine the\n> + * number of cores by from level type (ecx[15:8] == * 2)\n> + */\n> + if ((leaf_b.ecx & 0xff00) == 0x0200)\n> + return leaf_b.ebx & 0xffff;\n> +\n> + ecx++;\n> + }\n> +\n> + return 0;\n> +}\n> +\n> +static void braswell_set_max_freq(void)\n> +{\n> + msr_t perf_ctl;\n> + msr_t msr;\n> +\n> + /* Enable speed step */\n> + msr = msr_read(MSR_IA32_MISC_ENABLES);\n> + msr.lo |= (1 << 16);\n> + msr_write(MSR_IA32_MISC_ENABLES, msr);\n> +\n> + /* Enable Burst Mode */\n> + msr = msr_read(MSR_IA32_MISC_ENABLES);\n> + msr.hi = 0;\n> + msr_write(MSR_IA32_MISC_ENABLES, msr);\n> +\n> + /*\n> + * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to\n> + * bits [15:8] of the PERF_CTL\n> + */\n> + msr = msr_read(MSR_IACORE_TURBO_RATIOS);\n> + perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;\n> +\n> + /*\n> + * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to\n> + * bits [7:0] of the PERF_CTL\n> + */\n> + msr = msr_read(MSR_IACORE_TURBO_VIDS);\n> + perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;\n> +\n> + perf_ctl.hi = 0;\n> + msr_write(MSR_IA32_PERF_CTL, perf_ctl);\n> +}\n> +\n> +static int braswell_probe(struct udevice *dev)\n> +{\n> + debug(\"Init Braswell core\\n\");\n> +\n> + /*\n> + * On Braswell the turbo disable bit is actually scoped at the\n> + * building-block level, not package. For non-BSP cores that are\n> + * within a building block, enable turbo. The cores within the BSP's\n> + * building block will just see it already enabled and move on.\n> + */\n> + if (lapicid())\n> + turbo_enable();\n> +\n> + /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */\n> + msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),\n> + msr_clrsetbits_64(MSR_POWER_MISC,\n> + ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);\n> +\n> + /* Disable C1E */\n> + msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);\n> + msr_setbits_64(MSR_POWER_MISC, 0x44);\n> +\n> + /* Set this core to max frequency ratio */\n> + braswell_set_max_freq();\n> +\n> + return 0;\n> +}\n> +\n> +static const struct udevice_id braswell_ids[] = {\n> + { .compatible = \"intel,braswell-cpu\" },\n> + { }\n> +};\n> +\n> +static const struct cpu_ops braswell_ops = {\n> + .get_desc = cpu_x86_get_desc,\n> + .get_info = braswell_get_info,\n> + .get_count = braswell_get_count,\n> + .get_vendor = cpu_x86_get_vendor,\n> +};\n> +\n> +U_BOOT_DRIVER(cpu_x86_braswell_drv) = {\n> + .name = \"cpu_x86_braswell\",\n> + .id = UCLASS_CPU,\n> + .of_match = braswell_ids,\n> + .bind = cpu_x86_bind,\n> + .probe = braswell_probe,\n> + .ops = &braswell_ops,\n> +};\n> diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c\n> new file mode 100644\n> index 0000000..0300e13\n> --- /dev/null\n> +++ b/arch/x86/cpu/braswell/early_uart.c\n> @@ -0,0 +1,86 @@\n> +/*\n> + * Copyright (C) 2017, Bin Meng \n> + *\n> + * SPDX-License-Identifier: GPL-2.0+\n> + */\n> +\n> +#include \n> +#include \n> +\n> +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \\\n> + (((segbus) & 0xfff) << 20) | \\\n> + (((dev) & 0x1f) << 15) | \\\n> + (((fn) & 0x07) << 12))\n\nThis seems to be shared by baytrail? Do you think it should go in a header file?\n\n> +\n> +/* Platform Controller Unit */\n> +#define LPC_DEV 0x1f\n> +#define LPC_FUNC 0\n> +\n> +/* Enable UART */\n> +#define UART_CONT 0x80\n> +\n> +/* UART PAD definitions */\n> +#define UART_RXD_COMMUITY 1\n> +#define UART_TXD_COMMUITY 1\n> +#define UART_RXD_FAMILY 4\n> +#define UART_TXD_FAMILY 4\n> +#define UART_RXD_PAD 2\n> +#define UART_TXD_PAD 7\n> +#define UART_RXD_FUNC 3\n> +#define UART_TXD_FUNC 3\n> +\n> +/* IO Memory */\n> +#define IO_BASE_ADDRESS 0xfed80000\n> +\n> +static inline uint32_t gpio_pconf0(int community, int family, int pad)\n> +{\n> + return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +\n> + family * 0x400 + pad * 8;\n> +}\n> +\n> +static void gpio_select_func(int community, int family, int pad, int func)\n> +{\n> + uint32_t reg;\n> + uint32_t pconf0_addr = gpio_pconf0(community, family, pad);\n> +\n> + reg = readl(pconf0_addr);\n> + reg &= ~(0xf << 16);\n> + reg |= (func << 16);\n> + writel(reg, pconf0_addr);\n\nCan we use setclrbits_le32()?\n\n> +}\n> +\n> +static void x86_pci_write_config32(int dev, unsigned int where, u32 value)\n> +{\n> + unsigned long addr;\n> +\n> + addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);\n> + writel(value, addr);\n> +}\n> +\n\nRegards,\nSimon","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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\n\tSat, 26 Aug 2017 06:39:31 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1502862122-14771-10-git-send-email-bmeng.cn@gmail.com>","References":"<1502862122-14771-1-git-send-email-bmeng.cn@gmail.com>\n\t<1502862122-14771-10-git-send-email-bmeng.cn@gmail.com>","From":"Simon Glass ","Date":"Sat, 26 Aug 2017 07:39:10 -0600","X-Google-Sender-Auth":"u04c2fYNPvBJ3fGLojEVkzb-s4k","Message-ID":"","To":"Bin Meng ","Cc":"U-Boot Mailing List ","Subject":"Re: [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1758044,"web_url":"http://patchwork.ozlabs.org/comment/1758044/","msgid":"","list_archive_url":null,"date":"2017-08-26T13:55:04","subject":"Re: [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"content":"Hi Simon,\n\nOn Sat, Aug 26, 2017 at 9:39 PM, Simon Glass wrote:\n> On 15 August 2017 at 23:41, Bin Meng wrote:\n>> This adds initial Intel Braswell SoC support. It uses Intel FSP\n>> to initialize the chipset.\n>>\n>> Similar to its predecessor BayTrail, there are some work to do to\n>> enable the legacy UART integrated in the Braswell SoC.\n>>\n>> Signed-off-by: Bin Meng \n>> ---\n>>\n>> arch/x86/Kconfig | 1 +\n>> arch/x86/cpu/Makefile | 1 +\n>> arch/x86/cpu/braswell/Kconfig | 38 +++++++\n>> arch/x86/cpu/braswell/Makefile | 7 ++\n>> arch/x86/cpu/braswell/braswell.c | 36 ++++++\n>> arch/x86/cpu/braswell/cpu.c | 170 +++++++++++++++++++++++++++++\n>> arch/x86/cpu/braswell/early_uart.c | 86 +++++++++++++++\n>> arch/x86/include/asm/arch-braswell/iomap.h | 50 +++++++++\n>> 8 files changed, 389 insertions(+)\n>> create mode 100644 arch/x86/cpu/braswell/Kconfig\n>> create mode 100644 arch/x86/cpu/braswell/Makefile\n>> create mode 100644 arch/x86/cpu/braswell/braswell.c\n>> create mode 100644 arch/x86/cpu/braswell/cpu.c\n>> create mode 100644 arch/x86/cpu/braswell/early_uart.c\n>> create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h\n>\n> Reviewed-by: Simon Glass \n>\n> A few nits / suggestions below.\n>\n>>\n>> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig\n>> index f72d307..9620764 100644\n>> --- a/arch/x86/Kconfig\n>> +++ b/arch/x86/Kconfig\n>> @@ -108,6 +108,7 @@ source \"board/intel/Kconfig\"\n>>\n>> # platform-specific options below\n>> source \"arch/x86/cpu/baytrail/Kconfig\"\n>> +source \"arch/x86/cpu/braswell/Kconfig\"\n>> source \"arch/x86/cpu/broadwell/Kconfig\"\n>> source \"arch/x86/cpu/coreboot/Kconfig\"\n>> source \"arch/x86/cpu/ivybridge/Kconfig\"\n>> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile\n>> index 999429e..94cdff1 100644\n>> --- a/arch/x86/cpu/Makefile\n>> +++ b/arch/x86/cpu/Makefile\n>> @@ -27,6 +27,7 @@ endif\n>>\n>> obj-y += intel_common/\n>> obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/\n>> +obj-$(CONFIG_INTEL_BRASWELL) += braswell/\n>> obj-$(CONFIG_INTEL_BROADWELL) += broadwell/\n>> obj-$(CONFIG_SYS_COREBOOT) += coreboot/\n>> obj-$(CONFIG_EFI_APP) += efi/\n>> diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig\n>> new file mode 100644\n>> index 0000000..c993889\n>> --- /dev/null\n>> +++ b/arch/x86/cpu/braswell/Kconfig\n>> @@ -0,0 +1,38 @@\n>> +#\n>> +# Copyright (C) 2017, Bin Meng \n>> +#\n>> +# SPDX-License-Identifier: GPL-2.0+\n>> +#\n>> +\n>> +config INTEL_BRASWELL\n>> + bool\n>> + select HAVE_FSP\n>> + select ARCH_MISC_INIT\n>> + imply HAVE_INTEL_ME\n>> + imply HAVE_VBT\n>> + imply ENABLE_MRC_CACHE\n>> + imply ENV_IS_IN_SPI_FLASH\n>> + imply AHCI_PCI\n>> + imply ICH_SPI\n>> + imply MMC\n>> + imply MMC_PCI\n>> + imply MMC_SDHCI\n>> + imply MMC_SDHCI_SDMA\n>> + imply SCSI\n>> + imply SPI_FLASH\n>> + imply SYS_NS16550\n>> + imply USB\n>> + imply USB_XHCI_HCD\n>> + imply VIDEO_FSP\n>> +\n>> +if INTEL_BRASWELL\n>> +\n>> +config FSP_ADDR\n>> + hex\n>> + default 0xfff20000\n>> +\n>> +config FSP_LOCKDOWN_SPI\n>> + bool\n>> + default y\n>> +\n>> +endif\n>> diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile\n>> new file mode 100644\n>> index 0000000..19bcee6\n>> --- /dev/null\n>> +++ b/arch/x86/cpu/braswell/Makefile\n>> @@ -0,0 +1,7 @@\n>> +#\n>> +# Copyright (C) 2017, Bin Meng \n>> +#\n>> +# SPDX-License-Identifier: GPL-2.0+\n>> +#\n>> +\n>> +obj-y += braswell.o cpu.o early_uart.o\n>> diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c\n>> new file mode 100644\n>> index 0000000..37099aa\n>> --- /dev/null\n>> +++ b/arch/x86/cpu/braswell/braswell.c\n>> @@ -0,0 +1,36 @@\n>> +/*\n>> + * Copyright (C) 2017, Bin Meng \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0+\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +int arch_cpu_init(void)\n>> +{\n>> + post_code(POST_CPU_INIT);\n>> +\n>> + return x86_cpu_init_f();\n>> +}\n>> +\n>> +int arch_misc_init(void)\n>> +{\n>> +#ifdef CONFIG_ENABLE_MRC_CACHE\n>> + /*\n>> + * We intend not to check any return value here, as even MRC cache\n>> + * is not saved successfully, it is not a severe error that will\n>> + * prevent system from continuing to boot.\n>> + */\n>> + mrccache_save();\n>> +#endif\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +void reset_cpu(ulong addr)\n>> +{\n>> + /* cold reset */\n>> + x86_full_reset();\n>> +}\n>> diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c\n>> new file mode 100644\n>> index 0000000..6ff9036\n>> --- /dev/null\n>> +++ b/arch/x86/cpu/braswell/cpu.c\n>> @@ -0,0 +1,170 @@\n>> +/*\n>> + * Copyright (C) 2017, Bin Meng \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0+\n>> + *\n>> + * Derived from arch/x86/cpu/baytrail/cpu.c\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +static const unsigned int braswell_bus_freq_table[] = {\n>> + 83333333,\n>> + 100000000,\n>> + 133333333,\n>> + 116666666,\n>> + 80000000,\n>> + 93333333,\n>> + 90000000,\n>> + 88900000,\n>> + 87500000\n>> +};\n>> +\n>> +static unsigned int braswell_bus_freq(void)\n>> +{\n>> + msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);\n>> +\n>> + if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))\n>> + return braswell_bus_freq_table[clk_info.lo & 0xf];\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +static unsigned long braswell_tsc_freq(void)\n>> +{\n>> + msr_t platform_info;\n>> + ulong bclk = braswell_bus_freq();\n>> +\n>> + if (!bclk)\n>> + return 0;\n>> +\n>> + platform_info = msr_read(MSR_PLATFORM_INFO);\n>> +\n>> + return bclk * ((platform_info.lo >> 8) & 0xff);\n>> +}\n>> +\n>> +static int braswell_get_info(struct udevice *dev, struct cpu_info *info)\n>> +{\n>> + info->cpu_freq = braswell_tsc_freq();\n>> + info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +static int braswell_get_count(struct udevice *dev)\n>> +{\n>> + int ecx = 0;\n>> +\n>> + /*\n>> + * Use the algorithm described in Intel 64 and IA-32 Architectures\n>> + * Software Developer's Manual Volume 3 (3A, 3B & 3C): System\n>> + * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping\n>> + * of CPUID Extended Topology Leaf.\n>> + */\n>> + while (1) {\n>> + struct cpuid_result leaf_b;\n>> +\n>> + leaf_b = cpuid_ext(0xb, ecx);\n>> +\n>> + /*\n>> + * Braswell doesn't have hyperthreading so just determine the\n>> + * number of cores by from level type (ecx[15:8] == * 2)\n>> + */\n>> + if ((leaf_b.ecx & 0xff00) == 0x0200)\n>> + return leaf_b.ebx & 0xffff;\n>> +\n>> + ecx++;\n>> + }\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +static void braswell_set_max_freq(void)\n>> +{\n>> + msr_t perf_ctl;\n>> + msr_t msr;\n>> +\n>> + /* Enable speed step */\n>> + msr = msr_read(MSR_IA32_MISC_ENABLES);\n>> + msr.lo |= (1 << 16);\n>> + msr_write(MSR_IA32_MISC_ENABLES, msr);\n>> +\n>> + /* Enable Burst Mode */\n>> + msr = msr_read(MSR_IA32_MISC_ENABLES);\n>> + msr.hi = 0;\n>> + msr_write(MSR_IA32_MISC_ENABLES, msr);\n>> +\n>> + /*\n>> + * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to\n>> + * bits [15:8] of the PERF_CTL\n>> + */\n>> + msr = msr_read(MSR_IACORE_TURBO_RATIOS);\n>> + perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;\n>> +\n>> + /*\n>> + * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to\n>> + * bits [7:0] of the PERF_CTL\n>> + */\n>> + msr = msr_read(MSR_IACORE_TURBO_VIDS);\n>> + perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;\n>> +\n>> + perf_ctl.hi = 0;\n>> + msr_write(MSR_IA32_PERF_CTL, perf_ctl);\n>> +}\n>> +\n>> +static int braswell_probe(struct udevice *dev)\n>> +{\n>> + debug(\"Init Braswell core\\n\");\n>> +\n>> + /*\n>> + * On Braswell the turbo disable bit is actually scoped at the\n>> + * building-block level, not package. For non-BSP cores that are\n>> + * within a building block, enable turbo. The cores within the BSP's\n>> + * building block will just see it already enabled and move on.\n>> + */\n>> + if (lapicid())\n>> + turbo_enable();\n>> +\n>> + /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */\n>> + msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),\n>> + msr_clrsetbits_64(MSR_POWER_MISC,\n>> + ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);\n>> +\n>> + /* Disable C1E */\n>> + msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);\n>> + msr_setbits_64(MSR_POWER_MISC, 0x44);\n>> +\n>> + /* Set this core to max frequency ratio */\n>> + braswell_set_max_freq();\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +static const struct udevice_id braswell_ids[] = {\n>> + { .compatible = \"intel,braswell-cpu\" },\n>> + { }\n>> +};\n>> +\n>> +static const struct cpu_ops braswell_ops = {\n>> + .get_desc = cpu_x86_get_desc,\n>> + .get_info = braswell_get_info,\n>> + .get_count = braswell_get_count,\n>> + .get_vendor = cpu_x86_get_vendor,\n>> +};\n>> +\n>> +U_BOOT_DRIVER(cpu_x86_braswell_drv) = {\n>> + .name = \"cpu_x86_braswell\",\n>> + .id = UCLASS_CPU,\n>> + .of_match = braswell_ids,\n>> + .bind = cpu_x86_bind,\n>> + .probe = braswell_probe,\n>> + .ops = &braswell_ops,\n>> +};\n>> diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c\n>> new file mode 100644\n>> index 0000000..0300e13\n>> --- /dev/null\n>> +++ b/arch/x86/cpu/braswell/early_uart.c\n>> @@ -0,0 +1,86 @@\n>> +/*\n>> + * Copyright (C) 2017, Bin Meng \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0+\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +\n>> +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \\\n>> + (((segbus) & 0xfff) << 20) | \\\n>> + (((dev) & 0x1f) << 15) | \\\n>> + (((fn) & 0x07) << 12))\n>\n> This seems to be shared by baytrail? Do you think it should go in a header file?\n>\n\nYes, I think so.\n\n>> +\n>> +/* Platform Controller Unit */\n>> +#define LPC_DEV 0x1f\n>> +#define LPC_FUNC 0\n>> +\n>> +/* Enable UART */\n>> +#define UART_CONT 0x80\n>> +\n>> +/* UART PAD definitions */\n>> +#define UART_RXD_COMMUITY 1\n>> +#define UART_TXD_COMMUITY 1\n>> +#define UART_RXD_FAMILY 4\n>> +#define UART_TXD_FAMILY 4\n>> +#define UART_RXD_PAD 2\n>> +#define UART_TXD_PAD 7\n>> +#define UART_RXD_FUNC 3\n>> +#define UART_TXD_FUNC 3\n>> +\n>> +/* IO Memory */\n>> +#define IO_BASE_ADDRESS 0xfed80000\n>> +\n>> +static inline uint32_t gpio_pconf0(int community, int family, int pad)\n>> +{\n>> + return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +\n>> + family * 0x400 + pad * 8;\n>> +}\n>> +\n>> +static void gpio_select_func(int community, int family, int pad, int func)\n>> +{\n>> + uint32_t reg;\n>> + uint32_t pconf0_addr = gpio_pconf0(community, family, pad);\n>> +\n>> + reg = readl(pconf0_addr);\n>> + reg &= ~(0xf << 16);\n>> + reg |= (func << 16);\n>> + writel(reg, pconf0_addr);\n>\n> Can we use setclrbits_le32()?\n\nWill do in v2.\n\n>\n>> +}\n>> +\n>> +static void x86_pci_write_config32(int dev, unsigned int where, u32 value)\n>> +{\n>> + unsigned long addr;\n>> +\n>> + addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);\n>> + writel(value, addr);\n>> +}\n>> +\n\nRegards,\nBin","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1769556,"web_url":"http://patchwork.ozlabs.org/comment/1769556/","msgid":"","list_archive_url":null,"date":"2017-09-16T04:32:31","subject":"Re: [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"content":"On Sat, Aug 26, 2017 at 9:55 PM, Bin Meng wrote:\n> Hi Simon,\n>\n> On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass wrote:\n>> On 15 August 2017 at 23:41, Bin Meng wrote:\n>>> This adds initial Intel Braswell SoC support. It uses Intel FSP\n>>> to initialize the chipset.\n>>>\n>>> Similar to its predecessor BayTrail, there are some work to do to\n>>> enable the legacy UART integrated in the Braswell SoC.\n>>>\n>>> Signed-off-by: Bin Meng \n>>> ---\n>>>\n>>> arch/x86/Kconfig | 1 +\n>>> arch/x86/cpu/Makefile | 1 +\n>>> arch/x86/cpu/braswell/Kconfig | 38 +++++++\n>>> arch/x86/cpu/braswell/Makefile | 7 ++\n>>> arch/x86/cpu/braswell/braswell.c | 36 ++++++\n>>> arch/x86/cpu/braswell/cpu.c | 170 +++++++++++++++++++++++++++++\n>>> arch/x86/cpu/braswell/early_uart.c | 86 +++++++++++++++\n>>> arch/x86/include/asm/arch-braswell/iomap.h | 50 +++++++++\n>>> 8 files changed, 389 insertions(+)\n>>> create mode 100644 arch/x86/cpu/braswell/Kconfig\n>>> create mode 100644 arch/x86/cpu/braswell/Makefile\n>>> create mode 100644 arch/x86/cpu/braswell/braswell.c\n>>> create mode 100644 arch/x86/cpu/braswell/cpu.c\n>>> create mode 100644 arch/x86/cpu/braswell/early_uart.c\n>>> create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h\n>>\n>> Reviewed-by: Simon Glass \n>>\n>> A few nits / suggestions below.\n>>\n>>>\n\n[snip]\n\n>>> +static void gpio_select_func(int community, int family, int pad, int func)\n>>> +{\n>>> + uint32_t reg;\n>>> + uint32_t pconf0_addr = gpio_pconf0(community, family, pad);\n>>> +\n>>> + reg = readl(pconf0_addr);\n>>> + reg &= ~(0xf << 16);\n>>> + reg |= (func << 16);\n>>> + writel(reg, pconf0_addr);\n>>\n>> Can we use setclrbits_le32()?\n>\n> Will do in v2.\n>\n\nChanged to use clrsetbits_le32(), and\n\n>>\n>>> +}\n>>> +\n>>> +static void x86_pci_write_config32(int dev, unsigned int where, u32 value)\n>>> +{\n>>> + unsigned long addr;\n>>> +\n>>> + addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);\n>>> + writel(value, addr);\n>>> +}\n>>> +\n\napplied to u-boot-x86, thanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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