[{"id":1745901,"web_url":"http://patchwork.ozlabs.org/comment/1745901/","msgid":"<201708140112.bDMwr2ds%fengguang.wu@intel.com>","date":"2017-08-13T17:04:39","subject":"Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Alistair,\n\n[auto build test ERROR on powerpc/next]\n[also build test ERROR on v4.13-rc4 next-20170811]\n[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]\n\nurl: https://github.com/0day-ci/linux/commits/Alistair-Popple/powerpc-powernv-npu-Move-tlb-flush-before-launching-ATSD/20170813-211752\nbase: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next\nconfig: powerpc-defconfig (attached as .config)\ncompiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705\nreproduce:\n wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross\n chmod +x ~/bin/make.cross\n # save the attached .config to linux build tree\n make.cross ARCH=powerpc \n\nAll errors (new ones prefixed by >>):\n\n arch/powerpc/platforms/powernv/npu-dma.c: In function 'pnv_npu2_init_context':\n>> arch/powerpc/platforms/powernv/npu-dma.c:746:3: error: implicit declaration of function 'mm_context_set_global_tlbi' [-Werror=implicit-function-declaration]\n mm_context_set_global_tlbi(&mm->context);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n cc1: all warnings being treated as errors\n\nvim +/mm_context_set_global_tlbi +746 arch/powerpc/platforms/powernv/npu-dma.c\n\n 652\t\n 653\t/*\n 654\t * Call into OPAL to setup the nmmu context for the current task in\n 655\t * the NPU. This must be called to setup the context tables before the\n 656\t * GPU issues ATRs. pdev should be a pointed to PCIe GPU device.\n 657\t *\n 658\t * A release callback should be registered to allow a device driver to\n 659\t * be notified that it should not launch any new translation requests\n 660\t * as the final TLB invalidate is about to occur.\n 661\t *\n 662\t * Returns an error if there no contexts are currently available or a\n 663\t * npu_context which should be passed to pnv_npu2_handle_fault().\n 664\t *\n 665\t * mmap_sem must be held in write mode.\n 666\t */\n 667\tstruct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,\n 668\t\t\t\tunsigned long flags,\n 669\t\t\t\tstruct npu_context *(*cb)(struct npu_context *, void *),\n 670\t\t\t\tvoid *priv)\n 671\t{\n 672\t\tint rc;\n 673\t\tu32 nvlink_index;\n 674\t\tstruct device_node *nvlink_dn;\n 675\t\tstruct mm_struct *mm = current->mm;\n 676\t\tstruct pnv_phb *nphb;\n 677\t\tstruct npu *npu;\n 678\t\tstruct npu_context *npu_context;\n 679\t\n 680\t\t/*\n 681\t\t * At present we don't support GPUs connected to multiple NPUs and I'm\n 682\t\t * not sure the hardware does either.\n 683\t\t */\n 684\t\tstruct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);\n 685\t\n 686\t\tif (!firmware_has_feature(FW_FEATURE_OPAL))\n 687\t\t\treturn ERR_PTR(-ENODEV);\n 688\t\n 689\t\tif (!npdev)\n 690\t\t\t/* No nvlink associated with this GPU device */\n 691\t\t\treturn ERR_PTR(-ENODEV);\n 692\t\n 693\t\tif (!mm || mm->context.id == 0) {\n 694\t\t\t/*\n 695\t\t\t * Kernel thread contexts are not supported and context id 0 is\n 696\t\t\t * reserved on the GPU.\n 697\t\t\t */\n 698\t\t\treturn ERR_PTR(-EINVAL);\n 699\t\t}\n 700\t\n 701\t\tnphb = pci_bus_to_host(npdev->bus)->private_data;\n 702\t\tnpu = &nphb->npu;\n 703\t\n 704\t\t/*\n 705\t\t * Setup the NPU context table for a particular GPU. These need to be\n 706\t\t * per-GPU as we need the tables to filter ATSDs when there are no\n 707\t\t * active contexts on a particular GPU.\n 708\t\t */\n 709\t\trc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,\n 710\t\t\t\t\tPCI_DEVID(gpdev->bus->number, gpdev->devfn));\n 711\t\tif (rc < 0)\n 712\t\t\treturn ERR_PTR(-ENOSPC);\n 713\t\n 714\t\t/*\n 715\t\t * We store the npu pci device so we can more easily get at the\n 716\t\t * associated npus.\n 717\t\t */\n 718\t\tnpu_context = mm->context.npu_context;\n 719\t\tif (!npu_context) {\n 720\t\t\tnpu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);\n 721\t\t\tif (!npu_context)\n 722\t\t\t\treturn ERR_PTR(-ENOMEM);\n 723\t\n 724\t\t\tmm->context.npu_context = npu_context;\n 725\t\t\tnpu_context->mm = mm;\n 726\t\t\tnpu_context->mn.ops = &nv_nmmu_notifier_ops;\n 727\t\t\t__mmu_notifier_register(&npu_context->mn, mm);\n 728\t\t\tkref_init(&npu_context->kref);\n 729\t\t} else {\n 730\t\t\tkref_get(&npu_context->kref);\n 731\t\t}\n 732\t\n 733\t\tnpu_context->release_cb = cb;\n 734\t\tnpu_context->priv = priv;\n 735\t\tnvlink_dn = of_parse_phandle(npdev->dev.of_node, \"ibm,nvlink\", 0);\n 736\t\tif (WARN_ON(of_property_read_u32(nvlink_dn, \"ibm,npu-link-index\",\n 737\t\t\t\t\t\t\t\t&nvlink_index)))\n 738\t\t\treturn ERR_PTR(-ENODEV);\n 739\t\tnpu_context->npdev[npu->index][nvlink_index] = npdev;\n 740\t\n 741\t\tif (!nphb->npu.nmmu_flush)\n 742\t\t\t/*\n 743\t\t\t * If we're not explicitly flushing ourselves we need to mark\n 744\t\t\t * the thread for global flushes\n 745\t\t\t */\n > 746\t\t\tmm_context_set_global_tlbi(&mm->context);\n 747\t\n 748\t\treturn npu_context;\n 749\t}\n 750\tEXPORT_SYMBOL(pnv_npu2_init_context);\n 751\t\n\n---\n0-DAY kernel test infrastructure Open Source Technology Center\nhttps://lists.01.org/pipermail/kbuild-all Intel Corporation","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xVlX93Dnhz9s7F\n\tfor ;\n\tMon, 14 Aug 2017 03:06:49 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xVlX92GcMzDrJT\n\tfor ;\n\tMon, 14 Aug 2017 03:06:49 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xVlVn3sKfzDrD0\n\tfor ;\n\tMon, 14 Aug 2017 03:05:37 +1000 (AEST)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xVlVn3956z8sxs\n\tfor ;\n\tMon, 14 Aug 2017 03:05:37 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xVlVn2hLrz9sMN; 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