[{"id":1728595,"web_url":"http://patchwork.ozlabs.org/comment/1728595/","msgid":"<20170725143615.GA26029@nazgul.tnic>","date":"2017-07-25T14:36:15","subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","submitter":{"id":47897,"url":"http://patchwork.ozlabs.org/api/people/47897/","name":"Borislav Petkov","email":"bp@suse.de"},"content":"On Tue, Jul 25, 2017 at 09:29:40AM -0500, Tom Lendacky wrote:\n> Yup, we can do something like that. I believe the only change that\n> would be needed to your patch would be to move the IS_ENABLED() check\n> to after the physical address space reduction check.\n\nYeah, I wasn't sure about that. The logic is that if BIOS has enabled\nSME and thus reduction is in place, we need to update x86_phys_bits on\n32-bit regardless, right?\n\nBut, come to think of it, that reduction won't have any effect since we\nhave 32-bit addresses and the reduction is above 32-bits, right? And\nthus it is moot.\n\nOr?","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xH17Z2v4Jz9s7h\n\tfor ;\n\tWed, 26 Jul 2017 00:38:18 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xH17Z25nyzDqnQ\n\tfor ;\n\tWed, 26 Jul 2017 00:38:18 +1000 (AEST)","from mx1.suse.de (mx2.suse.de [195.135.220.15])\n\t(using TLSv1 with cipher ADH-CAMELLIA256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xH1672mSPzDqmj\n\tfor ;\n\tWed, 26 Jul 2017 00:37:02 +1000 (AEST)","from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254])\n\tby mx1.suse.de (Postfix) with ESMTP id BB639AE6E;\n\tTue, 25 Jul 2017 14:36:57 +0000 (UTC)"],"X-Virus-Scanned":"by amavisd-new at test-mx.suse.de","Date":"Tue, 25 Jul 2017 16:36:15 +0200","From":"Borislav Petkov ","To":"Tom Lendacky ","Subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","Message-ID":"<20170725143615.GA26029@nazgul.tnic>","References":"<20170724190757.11278-1-brijesh.singh@amd.com>\n\t<20170724190757.11278-3-brijesh.singh@amd.com>\n\t<20170725102657.GD21822@nazgul.tnic>\n\t<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>","User-Agent":"Mutt/1.6.0 (2016-04-01)","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-efi@vger.kernel.org, Brijesh Singh ,\n\tkvm@vger.kernel.org,\n\tRadim =?utf-8?B?S3LEjW3DocWZ?= , \n\tMatt Fleming ,\n\tDavid Howells , \n\tPaul Mackerras , \"H . Peter Anvin\" , \n\tChristoph Lameter , Jonathan Corbet ,\n\tx86@kernel.org, Piotr Luc ,\n\tIngo Molnar , Dave Airlie ,\n\tLaura Abbott , Fenghua Yu , \n\tKees Cook , Arnd Bergmann ,\n\tKonrad Rzeszutek Wilk ,\n\tReza Arbab ,\n\tAndy Lutomirski , \n\tThomas Gleixner , Tony Luck ,\n\tArd Biesheuvel ,\n\tlinux-kernel@vger.kernel.org, \n\tEric Biederman , Tejun Heo ,\n\tPaolo Bonzini ,\n\tAndrew Morton , \n\tlinuxppc-dev@lists.ozlabs.org,\n\t\"Kirill A . Shutemov\" ,\n\tLu Baolu ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1728601,"web_url":"http://patchwork.ozlabs.org/comment/1728601/","msgid":"<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>","date":"2017-07-25T14:29:40","subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","submitter":{"id":47310,"url":"http://patchwork.ozlabs.org/api/people/47310/","name":"Tom Lendacky","email":"Thomas.Lendacky@amd.com"},"content":"On 7/25/2017 5:26 AM, Borislav Petkov wrote:\n> On Mon, Jul 24, 2017 at 02:07:42PM -0500, Brijesh Singh wrote:\n>> From: Tom Lendacky \n>>\n>> Update the CPU features to include identifying and reporting on the\n>> Secure Encrypted Virtualization (SEV) feature. SME is identified by\n>> CPUID 0x8000001f, but requires BIOS support to enable it (set bit 23 of\n>> MSR_K8_SYSCFG and set bit 0 of MSR_K7_HWCR). Only show the SEV feature\n>> as available if reported by CPUID and enabled by BIOS.\n>>\n>> Signed-off-by: Tom Lendacky \n>> Signed-off-by: Brijesh Singh \n>> ---\n>> arch/x86/include/asm/cpufeatures.h | 1 +\n>> arch/x86/include/asm/msr-index.h | 2 ++\n>> arch/x86/kernel/cpu/amd.c | 30 +++++++++++++++++++++++++-----\n>> arch/x86/kernel/cpu/scattered.c | 1 +\n>> 4 files changed, 29 insertions(+), 5 deletions(-)\n> \n> ...\n> \n>> @@ -637,6 +642,21 @@ static void early_init_amd(struct cpuinfo_x86 *c)\n>> \t\t\tclear_cpu_cap(c, X86_FEATURE_SME);\n>> \t\t}\n>> \t}\n>> +\n>> +\tif (cpu_has(c, X86_FEATURE_SEV)) {\n>> +\t\tif (IS_ENABLED(CONFIG_X86_32)) {\n>> +\t\t\tclear_cpu_cap(c, X86_FEATURE_SEV);\n>> +\t\t} else {\n>> +\t\t\tu64 syscfg, hwcr;\n>> +\n>> +\t\t\t/* Check if SEV is enabled */\n>> +\t\t\trdmsrl(MSR_K8_SYSCFG, syscfg);\n>> +\t\t\trdmsrl(MSR_K7_HWCR, hwcr);\n>> +\t\t\tif (!(syscfg & MSR_K8_SYSCFG_MEM_ENCRYPT) ||\n>> +\t\t\t !(hwcr & MSR_K7_HWCR_SMMLOCK))\n>> +\t\t\t\tclear_cpu_cap(c, X86_FEATURE_SEV);\n>> +\t\t}\n>> +\t}\n> \n> Let's simplify this and read the MSRs only once. Diff ontop. Please\n> check if I'm missing a case:\n\nYup, we can do something like that. I believe the only change that\nwould be needed to your patch would be to move the IS_ENABLED() check\nto after the physical address space reduction check.\n\nThanks,\nTom\n\n> \n> ---\n> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c\n> index c413f04bdd41..79af07731ab1 100644\n> --- a/arch/x86/kernel/cpu/amd.c\n> +++ b/arch/x86/kernel/cpu/amd.c\n> @@ -546,6 +546,48 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)\n> \t}\n> }\n> \n> +static void early_detect_mem_enc(struct cpuinfo_x86 *c)\n> +{\n> +\tu64 syscfg, hwcr;\n> +\n> +\t/*\n> +\t * BIOS support is required for SME and SEV.\n> +\t * For SME: If BIOS has enabled SME then adjust x86_phys_bits by\n> +\t *\t the SME physical address space reduction value.\n> +\t *\t If BIOS has not enabled SME then don't advertise the\n> +\t *\t SME feature (set in scattered.c).\n> +\t * For SEV: If BIOS has not enabled SEV then don't advertise the\n> +\t * SEV feature (set in scattered.c).\n> +\t *\n> +\t * In all cases, since support for SME and SEV requires long mode,\n> +\t * don't advertise the feature under CONFIG_X86_32.\n> +\t */\n> +\tif (cpu_has(c, X86_FEATURE_SME) ||\n> +\t cpu_has(c, X86_FEATURE_SEV)) {\n> +\n> +\t\tif (IS_ENABLED(CONFIG_X86_32))\n> +\t\t\tgoto clear;\n> +\n> +\t\t/* Check if SME is enabled */\n> +\t\trdmsrl(MSR_K8_SYSCFG, syscfg);\n> +\t\tif (!(syscfg & MSR_K8_SYSCFG_MEM_ENCRYPT))\n> +\t\t\tgoto clear;\n> +\n> +\t\tc->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;\n> +\n> +\t\t/* Check if SEV is enabled */\n> +\t\trdmsrl(MSR_K7_HWCR, hwcr);\n> +\t\tif (!(hwcr & MSR_K7_HWCR_SMMLOCK))\n> +\t\t\tgoto clear_sev;\n> +\n> +\t\treturn;\n> +clear:\n> +\t\tclear_cpu_cap(c, X86_FEATURE_SME);\n> +clear_sev:\n> +\t\tclear_cpu_cap(c, X86_FEATURE_SEV);\n> +\t}\n> +}\n> +\n> static void early_init_amd(struct cpuinfo_x86 *c)\n> {\n> \tu32 dummy;\n> @@ -617,46 +659,8 @@ static void early_init_amd(struct cpuinfo_x86 *c)\n> \tif (cpu_has_amd_erratum(c, amd_erratum_400))\n> \t\tset_cpu_bug(c, X86_BUG_AMD_E400);\n> \n> -\t/*\n> -\t * BIOS support is required for SME and SEV.\n> -\t * For SME: If BIOS has enabled SME then adjust x86_phys_bits by\n> -\t *\t the SME physical address space reduction value.\n> -\t *\t If BIOS has not enabled SME then don't advertise the\n> -\t *\t SME feature (set in scattered.c).\n> -\t * For SEV: If BIOS has not enabled SEV then don't advertise the\n> -\t * SEV feature (set in scattered.c).\n> -\t *\n> -\t * In all cases, since support for SME and SEV requires long mode,\n> -\t * don't advertise the feature under CONFIG_X86_32.\n> -\t */\n> -\tif (cpu_has(c, X86_FEATURE_SME)) {\n> -\t\tu64 msr;\n> -\n> -\t\t/* Check if SME is enabled */\n> -\t\trdmsrl(MSR_K8_SYSCFG, msr);\n> -\t\tif (msr & MSR_K8_SYSCFG_MEM_ENCRYPT) {\n> -\t\t\tc->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;\n> -\t\t\tif (IS_ENABLED(CONFIG_X86_32))\n> -\t\t\t\tclear_cpu_cap(c, X86_FEATURE_SME);\n> -\t\t} else {\n> -\t\t\tclear_cpu_cap(c, X86_FEATURE_SME);\n> -\t\t}\n> -\t}\n> +\tearly_detect_mem_enc(c);\n> \n> -\tif (cpu_has(c, X86_FEATURE_SEV)) {\n> -\t\tif (IS_ENABLED(CONFIG_X86_32)) {\n> -\t\t\tclear_cpu_cap(c, X86_FEATURE_SEV);\n> -\t\t} else {\n> -\t\t\tu64 syscfg, hwcr;\n> -\n> -\t\t\t/* Check if SEV is enabled */\n> -\t\t\trdmsrl(MSR_K8_SYSCFG, syscfg);\n> -\t\t\trdmsrl(MSR_K7_HWCR, hwcr);\n> -\t\t\tif (!(syscfg & MSR_K8_SYSCFG_MEM_ENCRYPT) ||\n> -\t\t\t !(hwcr & MSR_K7_HWCR_SMMLOCK))\n> -\t\t\t\tclear_cpu_cap(c, X86_FEATURE_SEV);\n> -\t\t}\n> -\t}\n> }\n> \n> static void init_amd_k8(struct cpuinfo_x86 *c)\n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 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Add the Secure Encrypted\n\tVirtualization CPU feature","To":"Borislav Petkov , Brijesh Singh ","References":"<20170724190757.11278-1-brijesh.singh@amd.com>\n\t<20170724190757.11278-3-brijesh.singh@amd.com>\n\t<20170725102657.GD21822@nazgul.tnic>","From":"Tom Lendacky ","Message-ID":"<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>","Date":"Tue, 25 Jul 2017 09:29:40 -0500","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170725102657.GD21822@nazgul.tnic>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[165.204.78.1]","X-ClientProxiedBy":"CO2PR05CA0004.namprd05.prod.outlook.com (10.166.88.142) To\n\tDM5PR12MB1147.namprd12.prod.outlook.com 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not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"amd.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"25 Jul 2017 14:29:44.7336\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM5PR12MB1147","X-Mailman-Approved-At":"Wed, 26 Jul 2017 00:37:35 +1000","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-efi@vger.kernel.org, kvm@vger.kernel.org,\n\t=?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= ,\n\tMatt Fleming ,\n\tDavid Howells , \n\tPaul Mackerras , \"H . Peter Anvin\" , \n\tChristoph Lameter , Jonathan Corbet ,\n\tx86@kernel.org, Piotr Luc ,\n\tIngo Molnar , Dave Airlie ,\n\tLaura Abbott , Fenghua Yu , \n\tKees Cook , Arnd Bergmann ,\n\tKonrad Rzeszutek Wilk ,\n\tReza Arbab ,\n\tAndy Lutomirski , \n\tThomas Gleixner , Tony Luck ,\n\tArd Biesheuvel ,\n\tlinux-kernel@vger.kernel.org, \n\tEric Biederman , Tejun Heo ,\n\tPaolo Bonzini ,\n\tAndrew Morton , \n\tlinuxppc-dev@lists.ozlabs.org,\n\t\"Kirill A . Shutemov\" ,\n\tLu Baolu ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1728647,"web_url":"http://patchwork.ozlabs.org/comment/1728647/","msgid":"<47ccc32e-e113-48e0-d2e0-2f23b37cc452@amd.com>","date":"2017-07-25T14:58:54","subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","submitter":{"id":47310,"url":"http://patchwork.ozlabs.org/api/people/47310/","name":"Tom Lendacky","email":"Thomas.Lendacky@amd.com"},"content":"On 7/25/2017 9:36 AM, Borislav Petkov wrote:\n> On Tue, Jul 25, 2017 at 09:29:40AM -0500, Tom Lendacky wrote:\n>> Yup, we can do something like that. I believe the only change that\n>> would be needed to your patch would be to move the IS_ENABLED() check\n>> to after the physical address space reduction check.\n> \n> Yeah, I wasn't sure about that. The logic is that if BIOS has enabled\n> SME and thus reduction is in place, we need to update x86_phys_bits on\n> 32-bit regardless, right?\n> \n> But, come to think of it, that reduction won't have any effect since we\n> have 32-bit addresses and the reduction is above 32-bits, right? And\n> thus it is moot.\n\n\nTrue, but it is more about being accurate and making sure the value is\ncorrect where ever it may be used.\n\nThanks,\nTom\n\n> \n> Or?\n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xH1fJ69CHz9s72\n\tfor ;\n\tWed, 26 Jul 2017 01:01:28 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xH1fJ50cXzDqqQ\n\tfor ;\n\tWed, 26 Jul 2017 01:01:28 +1000 (AEST)","from NAM01-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam01on0077.outbound.protection.outlook.com [104.47.34.77])\n\t(using TLSv1.2 with cipher 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\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=Thomas.Lendacky@amd.com; "],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amdcloud.onmicrosoft.com; s=selector1-amd-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=cx42Zt6izcgSjheT5C+3zuOXlUjoLRl79r0KegnwobI=;\n\tb=0IiUx0220mRK9oDUnhn4SiTT0ufY3/tQhnU+CKejKKKjy98JfHliB2G1Mla4fxLwY3Ub4RYa0MLT+p8gRsI5HZObrzRJUZT2ghVdFXFW/AKaEuXGfRVxrU5KX+yeVlqpelOT67oONklpagL2mHJbvNu+LiG3CI5Wpw/lzbtWfjc=","Subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","To":"Borislav Petkov ","References":"<20170724190757.11278-1-brijesh.singh@amd.com>\n\t<20170724190757.11278-3-brijesh.singh@amd.com>\n\t<20170725102657.GD21822@nazgul.tnic>\n\t<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>\n\t<20170725143615.GA26029@nazgul.tnic>","From":"Tom Lendacky ","Message-ID":"<47ccc32e-e113-48e0-d2e0-2f23b37cc452@amd.com>","Date":"Tue, 25 Jul 2017 09:58:54 -0500","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170725143615.GA26029@nazgul.tnic>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[165.204.78.1]","X-ClientProxiedBy":"MWHPR1301CA0017.namprd13.prod.outlook.com (10.174.164.158)\n\tTo DM5PR12MB1147.namprd12.prod.outlook.com (10.168.236.142)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"fa0ea934-ab49-4924-9f4c-08d4d36db07d","X-MS-Office365-Filtering-HT":"Tenant","X-Microsoft-Antispam":"UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(48565401081)(201703131423075)(201703031133081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:DM5PR12MB1147; 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(protection.outlook.com: amd.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"amd.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"25 Jul 2017 14:58:59.2938\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM5PR12MB1147","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-efi@vger.kernel.org, Brijesh Singh ,\n\tkvm@vger.kernel.org,\n\t=?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , \n\tMatt Fleming ,\n\tDavid Howells , \n\tPaul Mackerras , \"H . Peter Anvin\" , \n\tChristoph Lameter , Jonathan Corbet ,\n\tx86@kernel.org, Piotr Luc ,\n\tIngo Molnar , Dave Airlie ,\n\tLaura Abbott , Fenghua Yu , \n\tKees Cook , Arnd Bergmann ,\n\tKonrad Rzeszutek Wilk ,\n\tReza Arbab ,\n\tAndy Lutomirski , \n\tThomas Gleixner , Tony Luck ,\n\tArd Biesheuvel ,\n\tlinux-kernel@vger.kernel.org, \n\tEric Biederman , Tejun Heo ,\n\tPaolo Bonzini ,\n\tAndrew Morton , \n\tlinuxppc-dev@lists.ozlabs.org,\n\t\"Kirill A . Shutemov\" ,\n\tLu Baolu ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1728668,"web_url":"http://patchwork.ozlabs.org/comment/1728668/","msgid":"<20170725151301.GC26029@nazgul.tnic>","date":"2017-07-25T15:13:01","subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","submitter":{"id":47897,"url":"http://patchwork.ozlabs.org/api/people/47897/","name":"Borislav Petkov","email":"bp@suse.de"},"content":"On Tue, Jul 25, 2017 at 09:58:54AM -0500, Tom Lendacky wrote:\n> True, but it is more about being accurate and making sure the value is\n> correct where ever it may be used.\n\nSo early_identify_cpu() initializes phys_bits to 32 on 32-bit.\nSubtracting it there would actually make actively it wrong, AFAICT.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xH1z147zJz9rxm\n\tfor ;\n\tWed, 26 Jul 2017 01:15:57 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xH1z12P1fzDqp8\n\tfor ;\n\tWed, 26 Jul 2017 01:15:57 +1000 (AEST)","from mx1.suse.de (mx2.suse.de [195.135.220.15])\n\t(using TLSv1 with cipher ADH-CAMELLIA256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xH1wS2ZL9zDqp8\n\tfor ;\n\tWed, 26 Jul 2017 01:13:44 +1000 (AEST)","from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254])\n\tby mx1.suse.de (Postfix) with ESMTP id DAECCAC1A;\n\tTue, 25 Jul 2017 15:13:40 +0000 (UTC)"],"X-Virus-Scanned":"by amavisd-new at test-mx.suse.de","Date":"Tue, 25 Jul 2017 17:13:01 +0200","From":"Borislav Petkov ","To":"Tom Lendacky ","Subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","Message-ID":"<20170725151301.GC26029@nazgul.tnic>","References":"<20170724190757.11278-1-brijesh.singh@amd.com>\n\t<20170724190757.11278-3-brijesh.singh@amd.com>\n\t<20170725102657.GD21822@nazgul.tnic>\n\t<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>\n\t<20170725143615.GA26029@nazgul.tnic>\n\t<47ccc32e-e113-48e0-d2e0-2f23b37cc452@amd.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<47ccc32e-e113-48e0-d2e0-2f23b37cc452@amd.com>","User-Agent":"Mutt/1.6.0 (2016-04-01)","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-efi@vger.kernel.org, Brijesh Singh ,\n\tkvm@vger.kernel.org,\n\tRadim =?utf-8?B?S3LEjW3DocWZ?= , \n\tMatt Fleming ,\n\tDavid Howells , \n\tPaul Mackerras , \"H . Peter Anvin\" , \n\tChristoph Lameter , Jonathan Corbet ,\n\tx86@kernel.org, Piotr Luc ,\n\tIngo Molnar , Dave Airlie ,\n\tLaura Abbott , Fenghua Yu , \n\tKees Cook , Arnd Bergmann ,\n\tKonrad Rzeszutek Wilk ,\n\tReza Arbab ,\n\tAndy Lutomirski , \n\tThomas Gleixner , Tony Luck ,\n\tArd Biesheuvel ,\n\tlinux-kernel@vger.kernel.org, \n\tEric Biederman , Tejun Heo ,\n\tPaolo Bonzini ,\n\tAndrew Morton , \n\tlinuxppc-dev@lists.ozlabs.org,\n\t\"Kirill A . Shutemov\" ,\n\tLu Baolu ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1728687,"web_url":"http://patchwork.ozlabs.org/comment/1728687/","msgid":"","date":"2017-07-25T15:29:40","subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","submitter":{"id":47310,"url":"http://patchwork.ozlabs.org/api/people/47310/","name":"Tom Lendacky","email":"Thomas.Lendacky@amd.com"},"content":"On 7/25/2017 10:13 AM, Borislav Petkov wrote:\n> On Tue, Jul 25, 2017 at 09:58:54AM -0500, Tom Lendacky wrote:\n>> True, but it is more about being accurate and making sure the value is\n>> correct where ever it may be used.\n> \n> So early_identify_cpu() initializes phys_bits to 32 on 32-bit.\n> Subtracting it there would actually make actively it wrong, AFAICT.\n\nBut early_identify_cpu() calls get_cpu_cap() which will check for cpuid\nleaf 0x80000008 support and set x86_phys_bits. I'll try to build and\nrun a 32-bit kernel and see how this all flows.\n\nThanks,\nTom\n\n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xH2KC3V4Kz9rxm\n\tfor ;\n\tWed, 26 Jul 2017 01:31:43 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xH2KC2JJNzDqnn\n\tfor ;\n\tWed, 26 Jul 2017 01:31:43 +1000 (AEST)","from NAM02-BL2-obe.outbound.protection.outlook.com\n\t(mail-bl2nam02on0056.outbound.protection.outlook.com [104.47.38.56])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby 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"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amdcloud.onmicrosoft.com; s=selector1-amd-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=rU6G095JB53l1MnZ1DS7SnqcTWE8QffdW1jVEgeeIq8=;\n\tb=WHFOxQ++Kxu2aXOzFFgd/ifGKsC+cvh7g1yblpcLW293XQFkfWUamUBbCEvd3ZInTkeYFJo/oo9JvoxGDHBhRaRQuZSyC2HTQhkOO7vARPhigC/gtzoCh/QAuCp00NoLQuvKRdbjzjFwiytT1Bpi6icrFPdtfuQqpmff1LMRkh4=","Subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","To":"Borislav Petkov ","References":"<20170724190757.11278-1-brijesh.singh@amd.com>\n\t<20170724190757.11278-3-brijesh.singh@amd.com>\n\t<20170725102657.GD21822@nazgul.tnic>\n\t<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>\n\t<20170725143615.GA26029@nazgul.tnic>\n\t<47ccc32e-e113-48e0-d2e0-2f23b37cc452@amd.com>\n\t<20170725151301.GC26029@nazgul.tnic>","From":"Tom Lendacky ","Message-ID":"","Date":"Tue, 25 Jul 2017 10:29:40 -0500","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; 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Peter Anvin\" , \n\tChristoph Lameter , Jonathan Corbet ,\n\tx86@kernel.org, Piotr Luc ,\n\tIngo Molnar , Dave Airlie ,\n\tLaura Abbott , Fenghua Yu , \n\tKees Cook , Arnd Bergmann ,\n\tKonrad Rzeszutek Wilk ,\n\tReza Arbab ,\n\tAndy Lutomirski , \n\tThomas Gleixner , Tony Luck ,\n\tArd Biesheuvel ,\n\tlinux-kernel@vger.kernel.org, \n\tEric Biederman , Tejun Heo ,\n\tPaolo Bonzini ,\n\tAndrew Morton , \n\tlinuxppc-dev@lists.ozlabs.org,\n\t\"Kirill A . Shutemov\" ,\n\tLu Baolu ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1728693,"web_url":"http://patchwork.ozlabs.org/comment/1728693/","msgid":"<20170725153329.GE26029@nazgul.tnic>","date":"2017-07-25T15:33:29","subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","submitter":{"id":47897,"url":"http://patchwork.ozlabs.org/api/people/47897/","name":"Borislav Petkov","email":"bp@suse.de"},"content":"On Tue, Jul 25, 2017 at 10:29:40AM -0500, Tom Lendacky wrote:\n> But early_identify_cpu() calls get_cpu_cap() which will check for cpuid\n> leaf 0x80000008 support and set x86_phys_bits.\n\nRight, but it can't be less than 32, can it? And if it is more than 32\nbits, then it probably doesn't really matter on 32-bit. Unless it is\nless than 36 bits and you do PAE...\n\n> I'll try to build and run a 32-bit kernel and see how this all flows.\n\nYeah, that would be good.\n\nThanks.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xH2Q01X3lz9ryr\n\tfor ;\n\tWed, 26 Jul 2017 01:35:52 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xH2Pz6dzYzDqq4\n\tfor ;\n\tWed, 26 Jul 2017 01:35:51 +1000 (AEST)","from mx1.suse.de (mx2.suse.de [195.135.220.15])\n\t(using TLSv1 with cipher ADH-CAMELLIA256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xH2NB0csmzDqp1\n\tfor ;\n\tWed, 26 Jul 2017 01:34:18 +1000 (AEST)","from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254])\n\tby mx1.suse.de (Postfix) with ESMTP id 68C0CAC1B;\n\tTue, 25 Jul 2017 15:34:13 +0000 (UTC)"],"X-Virus-Scanned":"by amavisd-new at test-mx.suse.de","Date":"Tue, 25 Jul 2017 17:33:29 +0200","From":"Borislav Petkov ","To":"Tom Lendacky ","Subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","Message-ID":"<20170725153329.GE26029@nazgul.tnic>","References":"<20170724190757.11278-1-brijesh.singh@amd.com>\n\t<20170724190757.11278-3-brijesh.singh@amd.com>\n\t<20170725102657.GD21822@nazgul.tnic>\n\t<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>\n\t<20170725143615.GA26029@nazgul.tnic>\n\t<47ccc32e-e113-48e0-d2e0-2f23b37cc452@amd.com>\n\t<20170725151301.GC26029@nazgul.tnic>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"","User-Agent":"Mutt/1.6.0 (2016-04-01)","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-efi@vger.kernel.org, Brijesh Singh ,\n\tkvm@vger.kernel.org,\n\tRadim =?utf-8?B?S3LEjW3DocWZ?= , \n\tMatt Fleming ,\n\tDavid Howells , \n\tPaul Mackerras , \"H . Peter Anvin\" , \n\tChristoph Lameter , Jonathan Corbet ,\n\tx86@kernel.org, Piotr Luc ,\n\tIngo Molnar , Dave Airlie ,\n\tLaura Abbott , Fenghua Yu , \n\tKees Cook , Arnd Bergmann ,\n\tKonrad Rzeszutek Wilk ,\n\tReza Arbab ,\n\tAndy Lutomirski , \n\tThomas Gleixner , Tony Luck ,\n\tArd Biesheuvel ,\n\tlinux-kernel@vger.kernel.org, \n\tEric Biederman , Tejun Heo ,\n\tPaolo Bonzini ,\n\tAndrew Morton , \n\tlinuxppc-dev@lists.ozlabs.org,\n\t\"Kirill A . Shutemov\" ,\n\tLu Baolu ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1743093,"web_url":"http://patchwork.ozlabs.org/comment/1743093/","msgid":"","date":"2017-08-09T18:17:54","subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","submitter":{"id":47310,"url":"http://patchwork.ozlabs.org/api/people/47310/","name":"Tom Lendacky","email":"Thomas.Lendacky@amd.com"},"content":"On 7/25/2017 10:33 AM, Borislav Petkov wrote:\n> On Tue, Jul 25, 2017 at 10:29:40AM -0500, Tom Lendacky wrote:\n>> But early_identify_cpu() calls get_cpu_cap() which will check for cpuid\n>> leaf 0x80000008 support and set x86_phys_bits.\n> \n> Right, but it can't be less than 32, can it? And if it is more than 32\n> bits, then it probably doesn't really matter on 32-bit. Unless it is\n> less than 36 bits and you do PAE...\n> \n>> I'll try to build and run a 32-bit kernel and see how this all flows.\n> \n> Yeah, that would be good.\n\nOk, finally got around to running a 32-bit kernel and it reports\nx86_phys_bits as 48.\n\nThanks,\nTom\n\n> \n> Thanks.\n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xSKMh5HGZz9s0g\n\tfor ;\n\tThu, 10 Aug 2017 04:21:04 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xSKMh36JjzDqr6\n\tfor ;\n\tThu, 10 Aug 2017 04:21:04 +1000 (AEST)","from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0083.outbound.protection.outlook.com\n\t[104.47.37.83])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xSKJX49GHzDqjk\n\tfor ;\n\tThu, 10 Aug 2017 04:18:20 +1000 (AEST)","from [10.236.64.250] (165.204.78.1) by\n\tBN6PR12MB1140.namprd12.prod.outlook.com (10.168.226.142) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.1.1320.16; Wed, 9 Aug 2017 18:18:04 +0000"],"Authentication-Results":["ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=amdcloud.onmicrosoft.com\n\theader.i=@amdcloud.onmicrosoft.com header.b=\"rqIcO7yl\"; \n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=amdcloud.onmicrosoft.com\n\theader.i=@amdcloud.onmicrosoft.com header.b=\"rqIcO7yl\"; \n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=amdcloud.onmicrosoft.com\n\theader.i=@amdcloud.onmicrosoft.com header.b=\"rqIcO7yl\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=Thomas.Lendacky@amd.com; "],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amdcloud.onmicrosoft.com; s=selector1-amd-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=9SZm9l1AUNgosQP/oZonxyMltGeNGnIth5VpsZvH5aQ=;\n\tb=rqIcO7yl1tpdkBf+Neq1rqMcC+y8BHHFc9E0IBkcVApLGmoNvnfQDaiFNrVlJc2aJx1tMtTxByKXw/GK0e7AxYun0MD5pubPd3sV/tn4eqp0Y40AXHI1e+IFkWX+CDlpefM4m2VXP73LNh0rbRlu7NoQ6bBLBfSb30NzvgSpwQo=","Subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","To":"Borislav Petkov ","References":"<20170724190757.11278-1-brijesh.singh@amd.com>\n\t<20170724190757.11278-3-brijesh.singh@amd.com>\n\t<20170725102657.GD21822@nazgul.tnic>\n\t<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>\n\t<20170725143615.GA26029@nazgul.tnic>\n\t<47ccc32e-e113-48e0-d2e0-2f23b37cc452@amd.com>\n\t<20170725151301.GC26029@nazgul.tnic>\n\t\n\t<20170725153329.GE26029@nazgul.tnic>","From":"Tom Lendacky ","Message-ID":"","Date":"Wed, 9 Aug 2017 13:17:54 -0500","User-Agent":"Mozilla/5.0 (Windows NT 10.0; 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SFP:1101; SCL:1; SRVR:BN6PR12MB1140; H:[10.236.64.250]; FPR:;\n\tSPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: amd.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"amd.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"09 Aug 2017 18:18:04.8694\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BN6PR12MB1140","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-efi@vger.kernel.org, Brijesh Singh ,\n\tkvm@vger.kernel.org,\n\t=?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , \n\tMatt Fleming ,\n\tDavid Howells , \n\tPaul Mackerras , \"H . Peter Anvin\" , \n\tChristoph Lameter , Jonathan Corbet ,\n\tx86@kernel.org, Piotr Luc ,\n\tIngo Molnar , Dave Airlie ,\n\tLaura Abbott , Fenghua Yu , \n\tKees Cook , Arnd Bergmann ,\n\tKonrad Rzeszutek Wilk ,\n\tReza Arbab ,\n\tAndy Lutomirski , \n\tThomas Gleixner , Tony Luck ,\n\tArd Biesheuvel ,\n\tlinux-kernel@vger.kernel.org, \n\tEric Biederman , Tejun Heo ,\n\tPaolo Bonzini ,\n\tAndrew Morton , \n\tlinuxppc-dev@lists.ozlabs.org,\n\t\"Kirill A . Shutemov\" ,\n\tLu Baolu ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1749329,"web_url":"http://patchwork.ozlabs.org/comment/1749329/","msgid":"<20170817081208.lmoh2dh3loupay54@pd.tnic>","date":"2017-08-17T08:12:08","subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","submitter":{"id":47897,"url":"http://patchwork.ozlabs.org/api/people/47897/","name":"Borislav Petkov","email":"bp@suse.de"},"content":"On Wed, Aug 09, 2017 at 01:17:54PM -0500, Tom Lendacky wrote:\n> Ok, finally got around to running a 32-bit kernel and it reports\n> x86_phys_bits as 48.\n\nSo it doesn't really matter on 32-bit. I guess you could add a comment\nsaying why we don't care.\n\nThanks.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xXzp550R8z9t2x\n\tfor ;\n\tThu, 17 Aug 2017 18:26:37 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xXzp545M1zDrJN\n\tfor ;\n\tThu, 17 Aug 2017 18:26:37 +1000 (AEST)","from mx1.suse.de (mx2.suse.de [195.135.220.15])\n\t(using TLSv1 with cipher ADH-CAMELLIA256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xXzmf0xTVzDrDC\n\tfor ;\n\tThu, 17 Aug 2017 18:25:21 +1000 (AEST)","from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254])\n\tby mx1.suse.de (Postfix) with ESMTP id E5220AD7F;\n\tThu, 17 Aug 2017 08:25:17 +0000 (UTC)"],"X-Virus-Scanned":"by amavisd-new at test-mx.suse.de","Date":"Thu, 17 Aug 2017 10:12:08 +0200","From":"Borislav Petkov ","To":"Tom Lendacky ","Subject":"Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted\n\tVirtualization CPU feature","Message-ID":"<20170817081208.lmoh2dh3loupay54@pd.tnic>","References":"<20170724190757.11278-1-brijesh.singh@amd.com>\n\t<20170724190757.11278-3-brijesh.singh@amd.com>\n\t<20170725102657.GD21822@nazgul.tnic>\n\t<7236d267-ebcb-8b45-b8d3-5955903e395f@amd.com>\n\t<20170725143615.GA26029@nazgul.tnic>\n\t<47ccc32e-e113-48e0-d2e0-2f23b37cc452@amd.com>\n\t<20170725151301.GC26029@nazgul.tnic>\n\t\n\t<20170725153329.GE26029@nazgul.tnic>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"","User-Agent":"NeoMutt/20170113 (1.7.2)","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-efi@vger.kernel.org, Brijesh Singh ,\n\tkvm@vger.kernel.org,\n\tRadim =?utf-8?B?S3LEjW3DocWZ?= , \n\tMatt Fleming ,\n\tDavid Howells , \n\tPaul Mackerras , \"H . Peter Anvin\" , \n\tChristoph Lameter , Jonathan Corbet ,\n\tx86@kernel.org, Piotr Luc ,\n\tIngo Molnar , Dave Airlie ,\n\tLaura Abbott , Fenghua Yu , \n\tKees Cook , Arnd Bergmann ,\n\tKonrad Rzeszutek Wilk ,\n\tReza Arbab ,\n\tAndy Lutomirski , \n\tThomas Gleixner , Tony Luck ,\n\tArd Biesheuvel ,\n\tlinux-kernel@vger.kernel.org, \n\tEric Biederman , Tejun Heo ,\n\tPaolo Bonzini ,\n\tAndrew Morton , \n\tlinuxppc-dev@lists.ozlabs.org,\n\t\"Kirill A . Shutemov\" ,\n\tLu Baolu ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}}]