[{"id":1711519,"web_url":"http://patchwork.ozlabs.org/comment/1711519/","msgid":"<87h8yo8un9.fsf@concordia.ellerman.id.au>","date":"2017-07-07T09:26:50","subject":"Re: [PATCH v12 01/10] powerpc/powernv: Data structure and macros\n\tdefinitions for IMC","submitter":{"id":46580,"url":"http://patchwork.ozlabs.org/api/people/46580/","name":"Michael Ellerman","email":"mpe@ellerman.id.au"},"content":"Hi Maddy/Anju,\n\nAnju T Sudhakar writes:\n> From: Madhavan Srinivasan \n>\n> Create a new header file to add the data structures and\n> macros needed for In-Memory Collection (IMC) counter support.\n>\n> Signed-off-by: Anju T Sudhakar \n> Signed-off-by: Hemant Kumar \n> Signed-off-by: Madhavan Srinivasan \n> ---\n> arch/powerpc/include/asm/imc-pmu.h | 99 ++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 99 insertions(+)\n> create mode 100644 arch/powerpc/include/asm/imc-pmu.h\n>\n> diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h\n> new file mode 100644\n> index 000000000000..ffaea0b9c13e\n> --- /dev/null\n> +++ b/arch/powerpc/include/asm/imc-pmu.h\n> @@ -0,0 +1,99 @@\n> +#ifndef PPC_POWERNV_IMC_PMU_DEF_H\n> +#define PPC_POWERNV_IMC_PMU_DEF_H\n> +\n> +/*\n> + * IMC Nest Performance Monitor counter support.\n> + *\n> + * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.\n> + * (C) 2017 Anju T Sudhakar, IBM Corporation.\n> + * (C) 2017 Hemant K Shaw, IBM Corporation.\n> + *\n> + * This program is free software; you can redistribute it and/or\n> + * modify it under the terms of the GNU General Public License\n> + * as published by the Free Software Foundation; either version\n> + * 2 of the License, or later version.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +/*\n> + * For static allocation of some of the structures.\n> + */\n> +#define IMC_MAX_PMUS\t\t\t32\n> +\n> +/*\n> + * This macro is used for memory buffer allocation of\n> + * event names and event string\n> + */\n> +#define IMC_MAX_NAME_VAL_LEN\t\t96\n> +\n> +/*\n> + * Currently Microcode supports a max of 256KB of counter memory\n> + * in the reserved memory region. Max pages to mmap (considering 4K PAGESIZE).\n> + */\n> +#define IMC_MAX_PAGES\t\t\t64\n\nIdeally that sort of detail comes from the device tree. Otherwise old\nkernels will be unable to run on new hardware which supports more memory.\n\nActually looking at where we use it, it seems like we don't it to come\nfrom the device tree.\n\nSeems core IMC only ever uses one page.\n\nThread IMC gets the size indirectly via the device tree:\n\n\tif (of_property_read_u32(parent, \"size\", &pmu_ptr->counter_mem_size))\n\nSo we should be able to dynamically size vbase.\n\n> +/*\n> + *Compatbility macros for IMC devices\n> + */\n> +#define IMC_DTB_COMPAT\t\t\t\"ibm,opal-in-memory-counters\"\n> +#define IMC_DTB_UNIT_COMPAT\t\t\"ibm,imc-counters\"\n> +\n> +/*\n> + * Structure to hold memory address information for imc units.\n> + */\n> +struct imc_mem_info {\n> +\tu32 id;\n> +\tu64 *vbase[IMC_MAX_PAGES];\n> +};\n\ncheers","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3x3q5n6HV4z9s4s\n\tfor ;\n\tFri, 7 Jul 2017 19:27:57 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3x3q5n5WsWzDr96\n\tfor ;\n\tFri, 7 Jul 2017 19:27:57 +1000 (AEST)","from ozlabs.org (ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3x3q4Y6D8fzDr5V\n\tfor ;\n\tFri, 7 Jul 2017 19:26:53 +1000 (AEST)","from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3x3q4Y428Fz9s7f;\n\tFri, 7 Jul 2017 19:26:53 +1000 (AEST)"],"From":"Michael Ellerman ","To":"Anju T Sudhakar ","Subject":"Re: [PATCH v12 01/10] powerpc/powernv: Data structure and macros\n\tdefinitions for IMC","In-Reply-To":"<1499074673-30576-2-git-send-email-anju@linux.vnet.ibm.com>","References":"<1499074673-30576-1-git-send-email-anju@linux.vnet.ibm.com>\n\t<1499074673-30576-2-git-send-email-anju@linux.vnet.ibm.com>","User-Agent":"Notmuch/0.21 (https://notmuchmail.org)","Date":"Fri, 07 Jul 2017 19:26:50 +1000","Message-ID":"<87h8yo8un9.fsf@concordia.ellerman.id.au>","MIME-Version":"1.0","Content-Type":"text/plain","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"stewart@linux.vnet.ibm.com, ego@linux.vnet.ibm.com, mikey@neuling.org,\n\tmaddy@linux.vnet.ibm.com, hemant@linux.vnet.ibm.com,\n\tlinux-kernel@vger.kernel.org, eranian@google.com,\n\tanju@linux.vnet.ibm.com, anton@samba.org, sukadev@linux.vnet.ibm.com,\n\tlinuxppc-dev@lists.ozlabs.org, dja@axtens.net","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}}]