[{"id":1527289,"web_url":"http://patchwork.ozlabs.org/comment/1527289/","msgid":"<201612051456.QmDg7mG4%fengguang.wu@intel.com>","date":"2016-12-05T06:59:39","subject":"Re: [PATCH v9] QE: remove PPCisms for QE","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Zhao,\n\n[auto build test ERROR on linus/master]\n[also build test ERROR on v4.9-rc8]\n[cannot apply to next-20161202]\n[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]\n\nurl: https://github.com/0day-ci/linux/commits/Zhao-Qiang/QE-remove-PPCisms-for-QE/20161205-131352\nconfig: i386-allmodconfig (attached as .config)\ncompiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901\nreproduce:\n # save the attached .config to linux build tree\n make ARCH=i386 \n\nAll errors (new ones prefixed by >>):\n\n In file included from drivers/soc/fsl/qe/qe_ic.c:31:0:\n include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_ipic':\n>> include/soc/fsl/qe/qe_ic.h:86:21: error: 'NO_IRQ' undeclared (first use in this function)\n if (cascade_irq != NO_IRQ)\n ^~~~~~\n include/soc/fsl/qe/qe_ic.h:86:21: note: each undeclared identifier is reported only once for each function it appears in\n include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_ipic':\n include/soc/fsl/qe/qe_ic.h:95:21: error: 'NO_IRQ' undeclared (first use in this function)\n if (cascade_irq != NO_IRQ)\n ^~~~~~\n include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_mpic':\n include/soc/fsl/qe/qe_ic.h:105:21: error: 'NO_IRQ' undeclared (first use in this function)\n if (cascade_irq != NO_IRQ)\n ^~~~~~\n include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_mpic':\n include/soc/fsl/qe/qe_ic.h:117:21: error: 'NO_IRQ' undeclared (first use in this function)\n if (cascade_irq != NO_IRQ)\n ^~~~~~\n include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_muxed_mpic':\n include/soc/fsl/qe/qe_ic.h:130:21: error: 'NO_IRQ' undeclared (first use in this function)\n if (cascade_irq == NO_IRQ)\n ^~~~~~\n drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_read':\n>> drivers/soc/fsl/qe/qe_ic.c:180:9: error: implicit declaration of function 'in_be32' [-Werror=implicit-function-declaration]\n return in_be32(base + (reg >> 2));\n ^~~~~~~\n drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_write':\n>> drivers/soc/fsl/qe/qe_ic.c:186:2: error: implicit declaration of function 'out_be32' [-Werror=implicit-function-declaration]\n out_be32(base + (reg >> 2), value);\n ^~~~~~~~\n drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_low_irq':\n>> drivers/soc/fsl/qe/qe_ic.c:299:10: error: 'NO_IRQ' undeclared (first use in this function)\n return NO_IRQ;\n ^~~~~~\n drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_high_irq':\n drivers/soc/fsl/qe/qe_ic.c:315:10: error: 'NO_IRQ' undeclared (first use in this function)\n return NO_IRQ;\n ^~~~~~\n drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_init':\n drivers/soc/fsl/qe/qe_ic.c:350:25: error: 'NO_IRQ' undeclared (first use in this function)\n if (qe_ic->virq_low == NO_IRQ) {\n ^~~~~~\n drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_set_highest_priority':\n>> drivers/soc/fsl/qe/qe_ic.c:392:21: error: implicit declaration of function 'virq_to_hw' [-Werror=implicit-function-declaration]\n unsigned int src = virq_to_hw(virq);\n ^~~~~~~~~~\n cc1: some warnings being treated as errors\n\nvim +/in_be32 +180 drivers/soc/fsl/qe/qe_ic.c\n\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 174 \t\t.pri_reg = QEIC_CIPYCC,\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 175 \t\t},\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 176 };\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 177 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 178 static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 179 {\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @180 \treturn in_be32(base + (reg >> 2));\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 181 }\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 182 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 183 static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 184 \t\t\t u32 value)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 185 {\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @186 \tout_be32(base + (reg >> 2), value);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 187 }\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 188 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 189 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 190 {\nec775d0e arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2011-03-25 191 \treturn irq_get_chip_data(virq);\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 192 }\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 193 \n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 194 static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 195 {\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 196 \treturn irq_data_get_irq_chip_data(d);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 197 }\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 198 \n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 199 static void qe_ic_unmask_irq(struct irq_data *d)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 200 {\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 201 \tstruct qe_ic *qe_ic = qe_ic_from_irq_data(d);\n476eb491 arch/powerpc/sysdev/qe_lib/qe_ic.c Grant Likely 2011-05-04 202 \tunsigned int src = irqd_to_hwirq(d);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 203 \tunsigned long flags;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 204 \tu32 temp;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 205 \n43a5a01b arch/powerpc/sysdev/qe_lib/qe_ic.c Anton Vorontsov 2010-02-18 206 \traw_spin_lock_irqsave(&qe_ic_lock, flags);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 207 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 208 \ttemp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 209 \tqe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 210 \t\t temp | qe_ic_info[src].mask);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 211 \n43a5a01b arch/powerpc/sysdev/qe_lib/qe_ic.c Anton Vorontsov 2010-02-18 212 \traw_spin_unlock_irqrestore(&qe_ic_lock, flags);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 213 }\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 214 \n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 215 static void qe_ic_mask_irq(struct irq_data *d)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 216 {\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 217 \tstruct qe_ic *qe_ic = qe_ic_from_irq_data(d);\n476eb491 arch/powerpc/sysdev/qe_lib/qe_ic.c Grant Likely 2011-05-04 218 \tunsigned int src = irqd_to_hwirq(d);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 219 \tunsigned long flags;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 220 \tu32 temp;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 221 \n43a5a01b arch/powerpc/sysdev/qe_lib/qe_ic.c Anton Vorontsov 2010-02-18 222 \traw_spin_lock_irqsave(&qe_ic_lock, flags);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 223 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 224 \ttemp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 225 \tqe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 226 \t\t temp & ~qe_ic_info[src].mask);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 227 \n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 228 \t/* Flush the above write before enabling interrupts; otherwise,\n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 229 \t * spurious interrupts will sometimes happen. To be 100% sure\n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 230 \t * that the write has reached the device before interrupts are\n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 231 \t * enabled, the mask register would have to be read back; however,\n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 232 \t * this is not required for correctness, only to avoid wasting\n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 233 \t * time on a large number of spurious interrupts. In testing,\n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 234 \t * a sync reduced the observed spurious interrupts to zero.\n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 235 \t */\n2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 236 \tmb();\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 237 \n43a5a01b arch/powerpc/sysdev/qe_lib/qe_ic.c Anton Vorontsov 2010-02-18 238 \traw_spin_unlock_irqrestore(&qe_ic_lock, flags);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 239 }\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 240 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 241 static struct irq_chip qe_ic_irq_chip = {\nb27df672 arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2009-11-18 242 \t.name = \"QEIC\",\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 243 \t.irq_unmask = qe_ic_unmask_irq,\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 244 \t.irq_mask = qe_ic_mask_irq,\n3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08 245 \t.irq_mask_ack = qe_ic_mask_irq,\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 246 };\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 247 \nad3aedfb arch/powerpc/sysdev/qe_lib/qe_ic.c Marc Zyngier 2015-07-28 248 static int qe_ic_host_match(struct irq_domain *h, struct device_node *node,\nad3aedfb arch/powerpc/sysdev/qe_lib/qe_ic.c Marc Zyngier 2015-07-28 249 \t\t\t enum irq_domain_bus_token bus_token)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 250 {\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 251 \t/* Exact match, unless qe_ic node is NULL */\n5d4c9bc7 arch/powerpc/sysdev/qe_lib/qe_ic.c Marc Zyngier 2015-10-13 252 \tstruct device_node *of_node = irq_domain_get_of_node(h);\n5d4c9bc7 arch/powerpc/sysdev/qe_lib/qe_ic.c Marc Zyngier 2015-10-13 253 \treturn of_node == NULL || of_node == node;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 254 }\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 255 \nbae1d8f1 arch/powerpc/sysdev/qe_lib/qe_ic.c Grant Likely 2012-02-14 256 static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 257 \t\t\t irq_hw_number_t hw)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 258 {\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 259 \tstruct qe_ic *qe_ic = h->host_data;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 260 \tstruct irq_chip *chip;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 261 \nc9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 262 \tif (hw >= ARRAY_SIZE(qe_ic_info)) {\nc9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 263 \t\tpr_err(\"%s: Invalid hw irq number for QEIC\\n\", __func__);\nc9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 264 \t\treturn -EINVAL;\nc9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 265 \t}\nc9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 266 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 267 \tif (qe_ic_info[hw].mask == 0) {\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 268 \t\tprintk(KERN_ERR \"Can't map reserved IRQ\\n\");\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 269 \t\treturn -EINVAL;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 270 \t}\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 271 \t/* Default chip */\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 272 \tchip = &qe_ic->hc_irq;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 273 \nec775d0e arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2011-03-25 274 \tirq_set_chip_data(virq, qe_ic);\n98488db9 arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2011-03-25 275 \tirq_set_status_flags(virq, IRQ_LEVEL);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 276 \nec775d0e arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2011-03-25 277 \tirq_set_chip_and_handler(virq, chip, handle_level_irq);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 278 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 279 \treturn 0;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 280 }\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 281 \n202648a6 arch/powerpc/sysdev/qe_lib/qe_ic.c Krzysztof Kozlowski 2015-04-27 282 static const struct irq_domain_ops qe_ic_host_ops = {\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 283 \t.match = qe_ic_host_match,\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 284 \t.map = qe_ic_host_map,\nff8c3ab8 arch/powerpc/sysdev/qe_lib/qe_ic.c Grant Likely 2012-01-24 285 \t.xlate = irq_domain_xlate_onetwocell,\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 286 };\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 287 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 288 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */\n35a84c2f arch/powerpc/sysdev/qe_lib/qe_ic.c Olaf Hering 2006-10-07 289 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 290 {\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 291 \tint irq;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 292 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 293 \tBUG_ON(qe_ic == NULL);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 294 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 295 \t/* get the interrupt source vector. */\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 296 \tirq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 297 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 298 \tif (irq == 0)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @299 \t\treturn NO_IRQ;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 300 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 301 \treturn irq_linear_revmap(qe_ic->irqhost, irq);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 302 }\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 303 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 304 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */\n35a84c2f arch/powerpc/sysdev/qe_lib/qe_ic.c Olaf Hering 2006-10-07 305 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 306 {\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 307 \tint irq;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 308 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 309 \tBUG_ON(qe_ic == NULL);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 310 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 311 \t/* get the interrupt source vector. */\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 312 \tirq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 313 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 314 \tif (irq == 0)\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @315 \t\treturn NO_IRQ;\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 316 \n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 317 \treturn irq_linear_revmap(qe_ic->irqhost, irq);\n98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 318 }\n\n:::::: The code at line 180 was first introduced by commit\n:::::: 9865853851313e0d94a4acde42d6f9d8070bb376 [POWERPC] Add QUICC Engine (QE) infrastructure\n\n:::::: TO: Li Yang \n:::::: CC: Paul Mackerras \n\n---\n0-DAY kernel test infrastructure Open Source Technology Center\nhttps://lists.01.org/pipermail/kbuild-all Intel Corporation","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3tXFzp5HV9z9t1d\n\tfor ;\n\tMon, 5 Dec 2016 18:01:42 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3tXFzp4TXTzDvxq\n\tfor ;\n\tMon, 5 Dec 2016 18:01:42 +1100 (AEDT)","from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3tXFyR3Hs8zDvjf\n\tfor ;\n\tMon, 5 Dec 2016 18:00:29 +1100 (AEDT)","from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga104.fm.intel.com with ESMTP; 04 Dec 2016 23:00:26 -0800","from bee.sh.intel.com (HELO bee) ([10.239.97.14])\n\tby fmsmga006.fm.intel.com with ESMTP; 04 Dec 2016 23:00:23 -0800","from kbuild by bee with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1cDnGs-000EGW-Qw; Mon, 05 Dec 2016 15:01:06 +0800"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.33,303,1477983600\"; \n\td=\"gz'50?scan'50,208,50\";a=\"38978172\"","Date":"Mon, 5 Dec 2016 14:59:39 +0800","From":"kbuild test robot ","To":"Zhao Qiang ","Subject":"Re: [PATCH v9] QE: remove PPCisms for QE","Message-ID":"<201612051456.QmDg7mG4%fengguang.wu@intel.com>","MIME-Version":"1.0","Content-Type":"multipart/mixed; boundary=\"Nq2Wo0NMKNjxTN9z\"","Content-Disposition":"inline","In-Reply-To":"<1480913809-23817-1-git-send-email-qiang.zhao@nxp.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-SA-Exim-Connect-IP":"","X-SA-Exim-Mail-From":"fengguang.wu@intel.com","X-SA-Exim-Scanned":"No (on bee); SAEximRunCond expanded to false","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"balbi@kernel.org, gregkh@linuxfoundation.org,\n\tlinux-kernel@vger.kernel.org, \n\txiaobo.xie@nxp.com, oss@buserror.net, kbuild-all@01.org,\n\tlinuxppc-dev@lists.ozlabs.org, Zhao Qiang ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1527302,"web_url":"http://patchwork.ozlabs.org/comment/1527302/","msgid":"","date":"2016-12-05T07:10:29","subject":"RE: [PATCH v9] QE: remove PPCisms for QE","submitter":{"id":68014,"url":"http://patchwork.ozlabs.org/api/people/68014/","name":"Qiang Zhao","email":"qiang.zhao@nxp.com"},"content":"This patch depends on the patchset of QEIC as following links:\n\thttp://patchwork.ozlabs.org/patch/675925/\n\thttp://patchwork.ozlabs.org/patch/675926/\n\thttp://patchwork.ozlabs.org/patch/675927/\n\thttp://patchwork.ozlabs.org/patch/675928/\n\n> -----Original Message-----\n> From: kbuild test robot [mailto:lkp@intel.com]\n> Sent: Monday, December 05, 2016 3:00 PM\n> To: Qiang Zhao \n> Cc: kbuild-all@01.org; oss@buserror.net; balbi@kernel.org;\n> gregkh@linuxfoundation.org; Xiaobo Xie ; linux-\n> kernel@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Qiang Zhao\n> \n> Subject: Re: [PATCH v9] QE: remove PPCisms for QE\n> \n> Hi Zhao,\n> \n> [auto build test ERROR on linus/master]\n> [also build test ERROR on v4.9-rc8]\n> [cannot apply to next-20161202]\n> [if your patch is applied to the wrong git tree, please drop us a note to help\n> improve the system]\n> \n> url: https://github.com/0day-ci/linux/commits/Zhao-Qiang/QE-remove-\n> PPCisms-for-QE/20161205-131352\n> config: i386-allmodconfig (attached as .config)\n> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901\n> reproduce:\n> # save the attached .config to linux build tree\n> make ARCH=i386\n> \n> All errors (new ones prefixed by >>):\n> \n> In file included from drivers/soc/fsl/qe/qe_ic.c:31:0:\n> include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_ipic':\n> >> include/soc/fsl/qe/qe_ic.h:86:21: error: 'NO_IRQ' undeclared (first use in\n> this function)\n> if (cascade_irq != NO_IRQ)\n> ^~~~~~\n> include/soc/fsl/qe/qe_ic.h:86:21: note: each undeclared identifier is reported\n> only once for each function it appears in\n> include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_ipic':\n> include/soc/fsl/qe/qe_ic.h:95:21: error: 'NO_IRQ' undeclared (first use in this\n> function)\n> if (cascade_irq != NO_IRQ)\n> ^~~~~~\n> include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_mpic':\n> include/soc/fsl/qe/qe_ic.h:105:21: error: 'NO_IRQ' undeclared (first use in\n> this function)\n> if (cascade_irq != NO_IRQ)\n> ^~~~~~\n> include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_mpic':\n> include/soc/fsl/qe/qe_ic.h:117:21: error: 'NO_IRQ' undeclared (first use in\n> this function)\n> if (cascade_irq != NO_IRQ)\n> ^~~~~~\n> include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_muxed_mpic':\n> include/soc/fsl/qe/qe_ic.h:130:21: error: 'NO_IRQ' undeclared (first use in\n> this function)\n> if (cascade_irq == NO_IRQ)\n> ^~~~~~\n> drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_read':\n> >> drivers/soc/fsl/qe/qe_ic.c:180:9: error: implicit declaration of function\n> 'in_be32' [-Werror=implicit-function-declaration]\n> return in_be32(base + (reg >> 2));\n> ^~~~~~~\n> drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_write':\n> >> drivers/soc/fsl/qe/qe_ic.c:186:2: error: implicit declaration of function\n> 'out_be32' [-Werror=implicit-function-declaration]\n> out_be32(base + (reg >> 2), value);\n> ^~~~~~~~\n> drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_low_irq':\n> >> drivers/soc/fsl/qe/qe_ic.c:299:10: error: 'NO_IRQ' undeclared (first use in\n> this function)\n> return NO_IRQ;\n> ^~~~~~\n> drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_high_irq':\n> drivers/soc/fsl/qe/qe_ic.c:315:10: error: 'NO_IRQ' undeclared (first use in this\n> function)\n> return NO_IRQ;\n> ^~~~~~\n> drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_init':\n> drivers/soc/fsl/qe/qe_ic.c:350:25: error: 'NO_IRQ' undeclared (first use in this\n> function)\n> if (qe_ic->virq_low == NO_IRQ) {\n> ^~~~~~\n> drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_set_highest_priority':\n> >> drivers/soc/fsl/qe/qe_ic.c:392:21: error: implicit declaration of function\n> 'virq_to_hw' [-Werror=implicit-function-declaration]\n> unsigned int src = virq_to_hw(virq);\n> ^~~~~~~~~~\n> cc1: some warnings being treated as errors\n> \n> vim +/in_be32 +180 drivers/soc/fsl/qe/qe_ic.c\n> \n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 174\n> \t.pri_reg = QEIC_CIPYCC,\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 175\n> \t},\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 176 };\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 177\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 178\n> static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 179 {\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @180\n> \treturn in_be32(base + (reg >> 2));\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 181 }\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 182\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 183\n> static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int\n> reg,\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 184\n> \t\t u32 value)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 185 {\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @186\n> \tout_be32(base + (reg >> 2), value);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 187 }\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 188\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 189\n> static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 190 {\n> ec775d0e arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2011-03-25\n> 191 \treturn irq_get_chip_data(virq);\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 192 }\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 193\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 194 static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 195 {\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 196 \treturn irq_data_get_irq_chip_data(d);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 197 }\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 198\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 199 static void qe_ic_unmask_irq(struct irq_data *d)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 200 {\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 201 \tstruct qe_ic *qe_ic = qe_ic_from_irq_data(d);\n> 476eb491 arch/powerpc/sysdev/qe_lib/qe_ic.c Grant Likely 2011-05-04 202\n> \tunsigned int src = irqd_to_hwirq(d);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 203\n> \tunsigned long flags;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 204\n> \tu32 temp;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 205\n> 43a5a01b arch/powerpc/sysdev/qe_lib/qe_ic.c Anton Vorontsov 2010-02-18\n> 206 \traw_spin_lock_irqsave(&qe_ic_lock, flags);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 207\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 208\n> \ttemp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 209\n> \tqe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 210\n> \t temp | qe_ic_info[src].mask);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 211\n> 43a5a01b arch/powerpc/sysdev/qe_lib/qe_ic.c Anton Vorontsov 2010-02-18\n> 212 \traw_spin_unlock_irqrestore(&qe_ic_lock, flags);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 213 }\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 214\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 215 static void qe_ic_mask_irq(struct irq_data *d)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 216 {\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 217 \tstruct qe_ic *qe_ic = qe_ic_from_irq_data(d);\n> 476eb491 arch/powerpc/sysdev/qe_lib/qe_ic.c Grant Likely 2011-05-04 218\n> \tunsigned int src = irqd_to_hwirq(d);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 219\n> \tunsigned long flags;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 220\n> \tu32 temp;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 221\n> 43a5a01b arch/powerpc/sysdev/qe_lib/qe_ic.c Anton Vorontsov 2010-02-18\n> 222 \traw_spin_lock_irqsave(&qe_ic_lock, flags);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 223\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 224\n> \ttemp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 225\n> \tqe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 226\n> \t temp & ~qe_ic_info[src].mask);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 227\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 228\n> \t/* Flush the above write before enabling interrupts; otherwise,\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 229\n> \t * spurious interrupts will sometimes happen. To be 100% sure\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 230\n> \t * that the write has reached the device before interrupts are\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 231\n> \t * enabled, the mask register would have to be read back; however,\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 232\n> \t * this is not required for correctness, only to avoid wasting\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 233\n> \t * time on a large number of spurious interrupts. In testing,\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 234\n> \t * a sync reduced the observed spurious interrupts to zero.\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 235\n> \t */\n> 2c1d2f34 arch/powerpc/sysdev/qe_lib/qe_ic.c Scott Wood 2006-12-06 236\n> \tmb();\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 237\n> 43a5a01b arch/powerpc/sysdev/qe_lib/qe_ic.c Anton Vorontsov 2010-02-18\n> 238 \traw_spin_unlock_irqrestore(&qe_ic_lock, flags);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 239 }\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 240\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 241\n> static struct irq_chip qe_ic_irq_chip = {\n> b27df672 arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2009-11-18\n> 242 \t.name = \"QEIC\",\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 243 \t.irq_unmask = qe_ic_unmask_irq,\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 244 \t.irq_mask = qe_ic_mask_irq,\n> 3a0adfab arch/powerpc/sysdev/qe_lib/qe_ic.c Lennert Buytenhek 2011-03-08\n> 245 \t.irq_mask_ack = qe_ic_mask_irq,\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 246 };\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 247\n> ad3aedfb arch/powerpc/sysdev/qe_lib/qe_ic.c Marc Zyngier 2015-07-28\n> 248 static int qe_ic_host_match(struct irq_domain *h, struct device_node\n> *node,\n> ad3aedfb arch/powerpc/sysdev/qe_lib/qe_ic.c Marc Zyngier 2015-07-28\n> 249 \t\t\t enum irq_domain_bus_token bus_token)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 250 {\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 251\n> \t/* Exact match, unless qe_ic node is NULL */\n> 5d4c9bc7 arch/powerpc/sysdev/qe_lib/qe_ic.c Marc Zyngier 2015-10-13\n> 252 \tstruct device_node *of_node = irq_domain_get_of_node(h);\n> 5d4c9bc7 arch/powerpc/sysdev/qe_lib/qe_ic.c Marc Zyngier 2015-10-13\n> 253 \treturn of_node == NULL || of_node == node;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 254 }\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 255\n> bae1d8f1 arch/powerpc/sysdev/qe_lib/qe_ic.c Grant Likely 2012-02-14 256\n> static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 257\n> \t\t irq_hw_number_t hw)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 258 {\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 259\n> \tstruct qe_ic *qe_ic = h->host_data;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 260\n> \tstruct irq_chip *chip;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 261\n> c9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 262\n> \tif (hw >= ARRAY_SIZE(qe_ic_info)) {\n> c9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 263\n> \tpr_err(\"%s: Invalid hw irq number for QEIC\\n\", __func__);\n> c9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 264\n> \treturn -EINVAL;\n> c9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 265 \t}\n> c9ee69c5 drivers/soc/fsl/qe/qe_ic.c Zhao Qiang 2016-01-21 266\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 267\n> \tif (qe_ic_info[hw].mask == 0) {\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 268\n> \tprintk(KERN_ERR \"Can't map reserved IRQ\\n\");\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 269\n> \treturn -EINVAL;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 270 \t}\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 271\n> \t/* Default chip */\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 272\n> \tchip = &qe_ic->hc_irq;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 273\n> ec775d0e arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2011-03-25\n> 274 \tirq_set_chip_data(virq, qe_ic);\n> 98488db9 arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2011-03-25\n> 275 \tirq_set_status_flags(virq, IRQ_LEVEL);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 276\n> ec775d0e arch/powerpc/sysdev/qe_lib/qe_ic.c Thomas Gleixner 2011-03-25\n> 277 \tirq_set_chip_and_handler(virq, chip, handle_level_irq);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 278\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 279\n> \treturn 0;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 280 }\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 281\n> 202648a6 arch/powerpc/sysdev/qe_lib/qe_ic.c Krzysztof Kozlowski 2015-04-27\n> 282 static const struct irq_domain_ops qe_ic_host_ops = {\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 283\n> \t.match = qe_ic_host_match,\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 284\n> \t.map = qe_ic_host_map,\n> ff8c3ab8 arch/powerpc/sysdev/qe_lib/qe_ic.c Grant Likely 2012-01-24 285\n> \t.xlate = irq_domain_xlate_onetwocell,\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 286 };\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 287\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 288 /*\n> Return an interrupt vector or NO_IRQ if no interrupt is pending. */\n> 35a84c2f arch/powerpc/sysdev/qe_lib/qe_ic.c Olaf Hering 2006-10-07 289\n> unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 290 {\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 291\n> \tint irq;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 292\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 293\n> \tBUG_ON(qe_ic == NULL);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 294\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 295\n> \t/* get the interrupt source vector. */\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 296\n> \tirq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 297\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 298\n> \tif (irq == 0)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @299\n> \treturn NO_IRQ;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 300\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 301\n> \treturn irq_linear_revmap(qe_ic->irqhost, irq);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 302 }\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 303\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 304 /*\n> Return an interrupt vector or NO_IRQ if no interrupt is pending. */\n> 35a84c2f arch/powerpc/sysdev/qe_lib/qe_ic.c Olaf Hering 2006-10-07 305\n> unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 306 {\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 307\n> \tint irq;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 308\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 309\n> \tBUG_ON(qe_ic == NULL);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 310\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 311\n> \t/* get the interrupt source vector. */\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 312\n> \tirq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 313\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 314\n> \tif (irq == 0)\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @315\n> \treturn NO_IRQ;\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 316\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 317\n> \treturn irq_linear_revmap(qe_ic->irqhost, irq);\n> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 318 }\n> \n> :::::: The code at line 180 was first introduced by commit\n> :::::: 9865853851313e0d94a4acde42d6f9d8070bb376 [POWERPC] Add QUICC\n> Engine (QE) infrastructure\n> \n> :::::: TO: Li Yang \n> :::::: CC: Paul Mackerras \n> \n> ---\n> 0-DAY kernel test infrastructure Open Source Technology Center\n> https://lists.01.org/pipermail/kbuild-all Intel Corporation","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate 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