[{"id":3688730,"web_url":"http://patchwork.ozlabs.org/comment/3688730/","msgid":"","list_archive_url":null,"date":"2026-05-08T21:01:23","subject":"Re: [PATCH v3 25/32] target/mips: add Octeon LA* atomic instructions","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 5/8/26 10:12, James Hilliard wrote:\n> Implement the Octeon LA* read-modify-write atomic instruction family:\n> LAI/LAID, LAD/LADD, LAA/LAAD, LAS/LASD, LAC/LACD, and LAW/LAWD.\n> \n> These operations are architecturally distinct from SAA/SAAD and are used\n> by existing Octeon user-mode code for atomic counters, bit operations,\n> and exchange-style updates.\n> \n> Signed-off-by: James Hilliard \n> ---\n> Changes v1 -> v2:\n> - Keep LA* atomics naturally aligned per Octeon L2 transaction\n> semantics.\n> - Use explicit i64 TCG ops in the LA* translator paths. (suggested by\n> Philippe Mathieu-Daudé)\n> \n> Changes v2 -> v3:\n> - Drop redundant TARGET_LONG_BITS guards from doubleword atomic paths.\n> (suggested by Richard Henderson)\n> - Group LA* translator wrappers by argument shape instead of adding one\n> wrapper per instruction. (suggested by Richard Henderson)\n> ---\n> target/mips/tcg/octeon.decode | 17 ++++++\n> target/mips/tcg/octeon_translate.c | 118 +++++++++++++++++++++++++++++++++++++\n> 2 files changed, 135 insertions(+)\n> \n> diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\n> index 54ca92a654..6f4102044f 100644\n> --- a/target/mips/tcg/octeon.decode\n> +++ b/target/mips/tcg/octeon.decode\n> @@ -59,6 +59,23 @@ V3MULU 011100 ..... ..... ..... 00000 010001 @r3\n> SAA 011100 ..... ..... 00000 00000 011000 @saa\n> SAAD 011100 ..... ..... 00000 00000 011001 @saa\n> \n> +&la base rd\n> +&laa base add rd\n> +@la ...... base:5 ..... rd:5 ........... &la\n> +@laa ...... base:5 add:5 rd:5 ........... &laa\n> +LAI 011100 ..... 00000 ..... 00010 011111 @la\n> +LAID 011100 ..... 00000 ..... 00011 011111 @la\n> +LAD 011100 ..... 00000 ..... 00110 011111 @la\n> +LADD 011100 ..... 00000 ..... 00111 011111 @la\n> +LAA 011100 ..... ..... ..... 10010 011111 @laa\n> +LAAD 011100 ..... ..... ..... 10011 011111 @laa\n> +LAS 011100 ..... 00000 ..... 01010 011111 @la\n> +LASD 011100 ..... 00000 ..... 01011 011111 @la\n> +LAC 011100 ..... 00000 ..... 01110 011111 @la\n> +LACD 011100 ..... 00000 ..... 01111 011111 @la\n> +LAW 011100 ..... ..... ..... 10110 011111 @laa\n> +LAWD 011100 ..... ..... ..... 10111 011111 @laa\n> +\n> &zcb base\n> ZCB 011100 base:5 00000 00000 11100 011111 &zcb\n> ZCBT 011100 base:5 00000 00000 11101 011111 &zcb\n> diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\n> index fe1ddeb973..cdaa926389 100644\n> --- a/target/mips/tcg/octeon_translate.c\n> +++ b/target/mips/tcg/octeon_translate.c\n> @@ -189,6 +189,112 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)\n> return true;\n> }\n> \n> +static bool trans_la_common(DisasContext *ctx, int base, int add_reg, int rd,\n> + int64_t imm, bool dw)\n> +{\n> + TCGv_i64 addr = tcg_temp_new_i64();\n> +\n> + gen_base_offset_addr(ctx, addr, base, 0);\n> +\n> + if (dw) {\n> + TCGv_i64 value = tcg_temp_new_i64();\n> + TCGv_i64 old = tcg_temp_new_i64();\n> + MemOp amo = mo_endian(ctx) | MO_UQ | MO_ALIGN;\n> +\n> + if (add_reg >= 0) {\n> + gen_load_gpr(value, add_reg);\n> + } else {\n> + tcg_gen_movi_i64(value, imm);\n> + }\n> +\n> + tcg_gen_atomic_fetch_add_i64(old, addr, value, ctx->mem_idx, amo);\n> + gen_store_gpr(old, rd);\n> + } else {\n> + TCGv_i64 old = tcg_temp_new_i64();\n> + TCGv_i32 value32 = tcg_temp_new_i32();\n> + TCGv_i32 old32 = tcg_temp_new_i32();\n> + MemOp amo = mo_endian(ctx) | MO_UL | MO_ALIGN;\n> +\n> + if (add_reg < 0) {\n> + tcg_gen_movi_i32(value32, imm);\n> + } else {\n> + TCGv_i64 value = tcg_temp_new_i64();\n> +\n> + gen_load_gpr(value, add_reg);\n> + tcg_gen_extrl_i64_i32(value32, value);\n> + }\n> +\n> + tcg_gen_atomic_fetch_add_i32(old32, addr, value32, ctx->mem_idx, amo);\n> + tcg_gen_ext_i32_i64(old, old32);\n> + gen_store_gpr(old, rd);\n> + }\n\nAlways use tcg_gen_atomic_fetch_add_i64.\n\nThe correct memop for 32-bit is MO_SL, so that you automatically get the sign-extension \nfor the 32-bit operation.\n\nWhich means that it'd be cleaner to replace the 'bool dw' parameter with 'MemOp mop'.\n\n> +static bool trans_law_common(DisasContext *ctx, int base, int add_reg, int rd,\n> + int64_t imm, bool dw)\n> +{\n> + TCGv_i64 addr = tcg_temp_new_i64();\n> +\n> + gen_base_offset_addr(ctx, addr, base, 0);\n> +\n> + if (dw) {\n> + TCGv_i64 value = tcg_temp_new_i64();\n> + TCGv_i64 old = tcg_temp_new_i64();\n> + MemOp amo = mo_endian(ctx) | MO_UQ | MO_ALIGN;\n> +\n> + if (add_reg >= 0) {\n> + gen_load_gpr(value, add_reg);\n> + } else {\n> + tcg_gen_movi_i64(value, imm);\n> + }\n> +\n> + tcg_gen_atomic_xchg_i64(old, addr, value, ctx->mem_idx, amo);\n> + gen_store_gpr(old, rd);\n> + } else {\n> + TCGv_i64 old = tcg_temp_new_i64();\n> + TCGv_i32 value32 = tcg_temp_new_i32();\n> + TCGv_i32 old32 = tcg_temp_new_i32();\n> + MemOp amo = mo_endian(ctx) | MO_UL | MO_ALIGN;\n> +\n> + if (add_reg >= 0) {\n> + TCGv_i64 value = tcg_temp_new_i64();\n> +\n> + gen_load_gpr(value, add_reg);\n> + tcg_gen_extrl_i64_i32(value32, value);\n> + } else {\n> + tcg_gen_movi_i32(value32, imm);\n> + }\n> +\n> + tcg_gen_atomic_xchg_i32(old32, addr, value32, ctx->mem_idx, amo);\n> + tcg_gen_ext_i32_i64(old, old32);\n> + gen_store_gpr(old, rd);\n> + }\n\nSimilarly.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=UXtt3eWT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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