[{"id":3688654,"web_url":"http://patchwork.ozlabs.org/comment/3688654/","msgid":"","list_archive_url":null,"date":"2026-05-08T17:56:21","subject":"Re: [PATCH v3 11/32] target/mips: add Octeon SAA instruction","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 5/8/26 10:12, James Hilliard wrote:\n> SAA atomically adds rt to the naturally aligned 32-bit word at base and\n> discards the old memory value.\n> \n> Implement it with TCG atomic_fetch_add_i32 using Octeon L2 transaction\n> alignment semantics.\n> \n> Signed-off-by: James Hilliard \n> ---\n> Changes v2 -> v3:\n> - Split SAA out of the combined Octeon arithmetic and memory\n> instruction patch. (requested by Richard Henderson)\n> ---\n> target/mips/tcg/octeon.decode | 4 ++++\n> target/mips/tcg/octeon_translate.c | 27 +++++++++++++++++++++++++++\n> 2 files changed, 31 insertions(+)\n> \n> diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\n> index db7d5f55f0..d6b241de42 100644\n> --- a/target/mips/tcg/octeon.decode\n> +++ b/target/mips/tcg/octeon.decode\n> @@ -44,6 +44,10 @@ SNE 011100 ..... ..... ..... 00000 101011 @r3\n> SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi\n> SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi\n> \n> +&saa base rt\n> +@saa ...... base:5 rt:5 ................ &saa\n> +SAA 011100 ..... ..... 00000 00000 011000 @saa\n> +\n> &lx base index rd\n> @lx ...... base:5 index:5 rd:5 ...... ..... &lx\n> LWX 011111 ..... ..... ..... 00000 001010 @lx\n> diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\n> index c93eff59a5..19535768d2 100644\n> --- a/target/mips/tcg/octeon_translate.c\n> +++ b/target/mips/tcg/octeon_translate.c\n> @@ -161,6 +161,33 @@ static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)\n> return true;\n> }\n> \n> +static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)\n> +{\n> + TCGv_i64 addr = tcg_temp_new_i64();\n> + MemOp amo = mo_endian(ctx) | mop | MO_ALIGN;\n> +\n> + gen_base_offset_addr(ctx, addr, a->base, 0);\n> +\n> + if (mop == MO_UQ) {\n> + TCGv_i64 value = tcg_temp_new_i64();\n> + TCGv_i64 old = tcg_temp_new_i64();\n> +\n> + gen_load_gpr(value, a->rt);\n> + tcg_gen_atomic_fetch_add_i64(old, addr, value, ctx->mem_idx, amo);\n> + } else {\n> + TCGv_i64 value = tcg_temp_new_i64();\n> + TCGv_i32 value32 = tcg_temp_new_i32();\n> + TCGv_i32 old = tcg_temp_new_i32();\n> +\n> + gen_load_gpr(value, a->rt);\n> + tcg_gen_extrl_i64_i32(value32, value);\n> + tcg_gen_atomic_fetch_add_i32(old, addr, value32, ctx->mem_idx, amo);\n> + }\n> +\n> + return true;\n> +}\n\nNo need to special-case UQ. You can always use tcg_gen_atomic_fetch_add_i64, which will \ndo the right thing based on mop.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=XtZyEPaW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBxdm2NmXz1yKd\n\tfor ; Sat, 09 May 2026 03:56:58 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLPRE-000771-VH; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::32c;\n envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3688659,"web_url":"http://patchwork.ozlabs.org/comment/3688659/","msgid":"<360a26b7-7591-401d-a6b5-21e1f4f2f597@linaro.org>","list_archive_url":null,"date":"2026-05-08T18:02:02","subject":"Re: [PATCH v3 11/32] target/mips: add Octeon SAA instruction","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 5/8/26 10:12, James Hilliard wrote:\n> SAA atomically adds rt to the naturally aligned 32-bit word at base and\n> discards the old memory value.\n> \n> Implement it with TCG atomic_fetch_add_i32 using Octeon L2 transaction\n> alignment semantics.\n> \n> Signed-off-by: James Hilliard \n> ---\n> Changes v2 -> v3:\n> - Split SAA out of the combined Octeon arithmetic and memory\n> instruction patch. (requested by Richard Henderson)\n> ---\n> target/mips/tcg/octeon.decode | 4 ++++\n> target/mips/tcg/octeon_translate.c | 27 +++++++++++++++++++++++++++\n> 2 files changed, 31 insertions(+)\n\nAccording to binutils, saa and saad are octeon+ instructions.\nWhich makes sense, because they aren't in my octeon docs.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=YHqr8f0y;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBxmt07M0z1yJq\n\tfor ; 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