[{"id":3688643,"web_url":"http://patchwork.ozlabs.org/comment/3688643/","msgid":"<92d5a546-7404-4866-a676-d970ce8bb6a1@linaro.org>","list_archive_url":null,"date":"2026-05-08T17:42:33","subject":"Re: [PATCH v3 07/32] target/mips: add Octeon multiplier state","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 5/8/26 10:12, James Hilliard wrote:\n> Add per-thread Octeon multiplier state for the MPL and P limb banks used\n> by the VMULU/VMM0/V3MULU instruction family.\n> \n> Keep the storage in uint64_t arrays and migrate it as an Octeon-only\n> subsection, so later instruction patches can update the architectural\n> multiplier state without mixing state layout changes with decode support.\n> \n> Signed-off-by: James Hilliard\n> ---\n> Changes v2 -> v3:\n> - Split the multiplier state out of the combined Octeon arithmetic and\n> memory instruction patch. (requested by Richard Henderson)\n> ---\n> target/mips/cpu.h | 4 ++++\n> target/mips/system/machine.c | 33 +++++++++++++++++++++++++++++++++\n> 2 files changed, 37 insertions(+)\n\nReviewed-by: Richard Henderson \n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=J+x02hM4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBxL135fdz1yJq\n\tfor ; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::331;\n envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3688668,"web_url":"http://patchwork.ozlabs.org/comment/3688668/","msgid":"<9dc3ea46-ddee-45b3-ad1a-c6d00dd98dc7@linaro.org>","list_archive_url":null,"date":"2026-05-08T18:17:10","subject":"Re: [PATCH v3 07/32] target/mips: add Octeon multiplier state","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 5/8/26 10:12, James Hilliard wrote:\n> Add per-thread Octeon multiplier state for the MPL and P limb banks used\n> by the VMULU/VMM0/V3MULU instruction family.\n> \n> Keep the storage in uint64_t arrays and migrate it as an Octeon-only\n> subsection, so later instruction patches can update the architectural\n> multiplier state without mixing state layout changes with decode support.\n> \n> Signed-off-by: James Hilliard \n> ---\n> Changes v2 -> v3:\n> - Split the multiplier state out of the combined Octeon arithmetic and\n> memory instruction patch. (requested by Richard Henderson)\n> ---\n> target/mips/cpu.h | 4 ++++\n> target/mips/system/machine.c | 33 +++++++++++++++++++++++++++++++++\n> 2 files changed, 37 insertions(+)\n> \n> diff --git a/target/mips/cpu.h b/target/mips/cpu.h\n> index 84d12b77f9..c6d75c67ab 100644\n> --- a/target/mips/cpu.h\n> +++ b/target/mips/cpu.h\n> @@ -497,6 +497,10 @@ struct TCState {\n> target_ulong CP0_TCScheFBack;\n> int32_t CP0_Debug_tcstatus;\n> target_ulong CP0_UserLocal;\n> + struct {\n> + uint64_t MPL[2 * 3];\n> + uint64_t P[2 * 3];\n> + } octeon;\n\nWhy are there 6 elements here?\nMy octeon documentation only says\n\nP0-P2 are 64-bit product registers. MPL0-MPL2 are 64-bit multiplier registers. Which \nmakes sense in the context of v3mulu \"192-bit x 64-bit unsigned multiply and add yielding \na 256-bit result\".\n\nDid this get copied from something that used uint32_t?\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=dMR4b0jw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBy676nyQz1yJq\n\tfor ; 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