[{"id":3688249,"web_url":"http://patchwork.ozlabs.org/comment/3688249/","msgid":"<42ec9559-3445-4712-bfd4-1319b4d4ce2d@intel.com>","list_archive_url":null,"date":"2026-05-08T09:36:01","subject":"Re: [PATCH v3 1/2] intel_iommu: fix guest-triggerable abort on\n oversized MMIO access","submitter":{"id":70117,"url":"http://patchwork.ozlabs.org/api/people/70117/","name":"Yi Liu","email":"yi.l.liu@intel.com"},"content":"On 5/6/26 11:19, Junjie Cao wrote:\n> An 8-byte guest access to a 32-bit-only VT-d register hit\n> assert(size == 4) and aborted QEMU. Remove all 25 asserts.\n> \n> 21 sit at non-8-byte-aligned offsets and are rejected by\n> memory_region_access_valid() before reaching the handler -- dead\n> code, simply deleted.\n> \n> The remaining 4 guard 8-byte-aligned 32-bit registers reachable\n> by a well-formed 8-byte access (FECTL 0x38, IECTL 0xa0, IEADDR\n> 0xa8, PECTL 0xe0). \n\ncould you share how you identify the 4 registers among all the\nregisters. The offset of such registers are multiple of 8? is it? Just\ncurious why only 4 registers.\n\n> Writes fall through to vtd_set_long(), which\n> takes uint32_t and implicitly truncates, and log a guest error.\n> Reads fall through to the default vtd_get_quad() -- equivalent\n> to two 4-byte reads and therefore harmless, no warn needed.\n> min_access_size stays 4, so all size-based branches on 64-bit\n> register pairs are preserved.\n> \n> Found by generic-fuzz (24 distinct crash seeds, all fixed).\n> \n> Suggested-by: Zhenzhong Duan \n> Signed-off-by: Junjie Cao \n> ---\n> hw/i386/intel_iommu.c | 41 ++++++++++++++++-------------------------\n> 1 file changed, 16 insertions(+), 25 deletions(-)\n> \n> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\n> index f395fa248c..0fb89332f9 100644\n> --- a/hw/i386/intel_iommu.c\n> +++ b/hw/i386/intel_iommu.c\n> @@ -3713,7 +3713,6 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n> break;\n> \n> case DMAR_RTADDR_REG_HI:\n> - assert(size == 4);\n> val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;\n> break;\n> \n> @@ -3728,12 +3727,10 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n> break;\n> \n> case DMAR_IQA_REG_HI:\n> - assert(size == 4);\n> val = s->iq >> 32;\n> break;\n> \n> case DMAR_PEUADDR_REG:\n> - assert(size == 4);\n> val = vtd_get_long_raw(s, DMAR_PEUADDR_REG);\n> break;\n> \n> @@ -3779,7 +3776,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_CCMD_REG_HI:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_ccmd_write(s);\n> break;\n> @@ -3795,13 +3791,11 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_IOTLB_REG_HI:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_iotlb_write(s);\n> break;\n> \n> case DMAR_PEUADDR_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> @@ -3815,27 +3809,27 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_IVA_REG_HI:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> /* Fault Status Register, 32-bit */\n> case DMAR_FSTS_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_fsts_write(s);\n> break;\n> \n> /* Fault Event Control Register, 32-bit */\n> case DMAR_FECTL_REG:\n> - assert(size == 4);\n> + if (size != 4) {\n> + error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n> + \"addr=0x%\" PRIx64, __func__, size, addr);\n> + }\n\nSince such writes are harmless, I don't think it is really helpful to\nhave this error log. Instead, we should have a comment here to avoid\nsomebody break it in future.\n\n> vtd_set_long(s, addr, val);\n> vtd_handle_fectl_write(s);\n> break;\n> \n> /* Fault Event Data Register, 32-bit */\n> case DMAR_FEDATA_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> @@ -3854,13 +3848,11 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> \n> /* Fault Event Upper Address Register, 32-bit */\n> case DMAR_FEUADDR_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> /* Protected Memory Enable Register, 32-bit */\n> case DMAR_PMEN_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> @@ -3874,7 +3866,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_RTADDR_REG_HI:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> @@ -3889,7 +3880,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_IQT_REG_HI:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> /* 19:63 of IQT_REG is RsvdZ, do nothing here */\n> break;\n> @@ -3905,39 +3895,41 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_IQA_REG_HI:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> /* Invalidation Completion Status Register, 32-bit */\n> case DMAR_ICS_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_ics_write(s);\n> break;\n> \n> /* Invalidation Event Control Register, 32-bit */\n> case DMAR_IECTL_REG:\n> - assert(size == 4);\n> + if (size != 4) {\n> + error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n> + \"addr=0x%\" PRIx64, __func__, size, addr);\n> + }\n> vtd_set_long(s, addr, val);\n> vtd_handle_iectl_write(s);\n> break;\n> \n> /* Invalidation Event Data Register, 32-bit */\n> case DMAR_IEDATA_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> /* Invalidation Event Address Register, 32-bit */\n> case DMAR_IEADDR_REG:\n> - assert(size == 4);\n> + if (size != 4) {\n> + error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n> + \"addr=0x%\" PRIx64, __func__, size, addr);\n> + }\n> vtd_set_long(s, addr, val);\n> break;\n> \n> /* Invalidation Event Upper Address Register, 32-bit */\n> case DMAR_IEUADDR_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> @@ -3951,7 +3943,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_FRCD_REG_0_1:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> @@ -3966,7 +3957,6 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_FRCD_REG_0_3:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> /* May clear bit 127 (Fault), update PPF */\n> vtd_update_fsts_ppf(s);\n> @@ -3981,18 +3971,19 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n> break;\n> \n> case DMAR_IRTA_REG_HI:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n> \n> case DMAR_PRS_REG:\n> - assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_prs_write(s);\n> break;\n> \n> case DMAR_PECTL_REG:\n> - assert(size == 4);\n> + if (size != 4) {\n> + error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n> + \"addr=0x%\" PRIx64, __func__, size, addr);\n> + }\n> vtd_set_long(s, addr, val);\n> vtd_handle_pectl_write(s);\n> break;","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=nBIEI8d/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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envelope-from=yi.l.liu@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-47","X-Spam_score":"-4.8","X-Spam_bar":"----","X-Spam_report":"(-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_NONE=0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3689035,"web_url":"http://patchwork.ozlabs.org/comment/3689035/","msgid":"","list_archive_url":null,"date":"2026-05-11T05:41:52","subject":"RE: [PATCH v3 1/2] intel_iommu: fix guest-triggerable abort on\n oversized MMIO access","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/people/81636/","name":"Zhenzhong Duan","email":"zhenzhong.duan@intel.com"},"content":">-----Original Message-----\n>From: Liu, Yi L \n>Subject: Re: [PATCH v3 1/2] intel_iommu: fix guest-triggerable abort on oversized\n>MMIO access\n>\n>On 5/6/26 11:19, Junjie Cao wrote:\n>> An 8-byte guest access to a 32-bit-only VT-d register hit\n>> assert(size == 4) and aborted QEMU. Remove all 25 asserts.\n>>\n>> 21 sit at non-8-byte-aligned offsets and are rejected by\n>> memory_region_access_valid() before reaching the handler -- dead\n>> code, simply deleted.\n>>\n>> The remaining 4 guard 8-byte-aligned 32-bit registers reachable\n>> by a well-formed 8-byte access (FECTL 0x38, IECTL 0xa0, IEADDR\n>> 0xa8, PECTL 0xe0).\n>\n>could you share how you identify the 4 registers among all the\n>registers. The offset of such registers are multiple of 8? is it? Just\n>curious why only 4 registers.\n>\n>> Writes fall through to vtd_set_long(), which\n>> takes uint32_t and implicitly truncates, and log a guest error.\n>> Reads fall through to the default vtd_get_quad() -- equivalent\n>> to two 4-byte reads and therefore harmless, no warn needed.\n>> min_access_size stays 4, so all size-based branches on 64-bit\n>> register pairs are preserved.\n>>\n>> Found by generic-fuzz (24 distinct crash seeds, all fixed).\n>>\n>> Suggested-by: Zhenzhong Duan \n>> Signed-off-by: Junjie Cao \n>> ---\n>> hw/i386/intel_iommu.c | 41 ++++++++++++++++-------------------------\n>> 1 file changed, 16 insertions(+), 25 deletions(-)\n>>\n>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\n>> index f395fa248c..0fb89332f9 100644\n>> --- a/hw/i386/intel_iommu.c\n>> +++ b/hw/i386/intel_iommu.c\n>> @@ -3713,7 +3713,6 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr\n>addr, unsigned size)\n>> break;\n>>\n>> case DMAR_RTADDR_REG_HI:\n>> - assert(size == 4);\n>> val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;\n>> break;\n>>\n>> @@ -3728,12 +3727,10 @@ static uint64_t vtd_mem_read(void *opaque,\n>hwaddr addr, unsigned size)\n>> break;\n>>\n>> case DMAR_IQA_REG_HI:\n>> - assert(size == 4);\n>> val = s->iq >> 32;\n>> break;\n>>\n>> case DMAR_PEUADDR_REG:\n>> - assert(size == 4);\n>> val = vtd_get_long_raw(s, DMAR_PEUADDR_REG);\n>> break;\n>>\n>> @@ -3779,7 +3776,6 @@ static void vtd_mem_write(void *opaque, hwaddr\n>addr,\n>> break;\n>>\n>> case DMAR_CCMD_REG_HI:\n>> - assert(size == 4);\n>> vtd_set_long(s, addr, val);\n>> vtd_handle_ccmd_write(s);\n>> break;\n>> @@ -3795,13 +3791,11 @@ static void vtd_mem_write(void *opaque, hwaddr\n>addr,\n>> break;\n>>\n>> case DMAR_IOTLB_REG_HI:\n>> - assert(size == 4);\n>> vtd_set_long(s, addr, val);\n>> vtd_handle_iotlb_write(s);\n>> break;\n>>\n>> case DMAR_PEUADDR_REG:\n>> - assert(size == 4);\n>> vtd_set_long(s, addr, val);\n>> break;\n>>\n>> @@ -3815,27 +3809,27 @@ static void vtd_mem_write(void *opaque, hwaddr\n>addr,\n>> break;\n>>\n>> case DMAR_IVA_REG_HI:\n>> - assert(size == 4);\n>> vtd_set_long(s, addr, val);\n>> break;\n>>\n>> /* Fault Status Register, 32-bit */\n>> case DMAR_FSTS_REG:\n>> - assert(size == 4);\n>> vtd_set_long(s, addr, val);\n>> vtd_handle_fsts_write(s);\n>> break;\n>>\n>> /* Fault Event Control Register, 32-bit */\n>> case DMAR_FECTL_REG:\n>> - assert(size == 4);\n>> + if (size != 4) {\n>> + error_report_once(\"%s: invalid %u-byte access to 32-bit reg \"\n>> + \"addr=0x%\" PRIx64, __func__, size, addr);\n>> + }\n>\n>Since such writes are harmless, I don't think it is really helpful to\n>have this error log. Instead, we should have a comment here to avoid\n>somebody break it in future.\n\nMaybe to take it as guest error and log it:\n\nqemu_log_mask(LOG_GUEST_ERROR,...),\n\nthen people could catch it and fix guest code?\n\nThanks\nZhenzhong","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=KzCpFfKU;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=intel.com;"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gDTCP4XPGz1yDx\n\tfor ; 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