[{"id":3686963,"web_url":"http://patchwork.ozlabs.org/comment/3686963/","msgid":"","list_archive_url":null,"date":"2026-05-06T10:38:15","subject":"Re: [PATCH v2 3/7] include/hw/hyperv: add hv_vp_register_page struct\n definition","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/people/90753/","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"content":"On Tue, May 05, 2026 at 09:50:24PM +0300, Doru Blânzeanu wrote:\n> Define the `hv_vp_register_page` structure that the linux kernel uses\n> to allow access to vcpu registers.\n> \n> This structure is going to be used in later patches to access vcpu\n> registers.\n> \n> Signed-off-by: Doru Blânzeanu \n> ---\n> include/hw/hyperv/hvgdk.h | 2 +\n> include/hw/hyperv/hvhdk.h | 105 ++++++++++++++++++++++++++++++++++++++\n> 2 files changed, 107 insertions(+)\n> \n> diff --git a/include/hw/hyperv/hvgdk.h b/include/hw/hyperv/hvgdk.h\n> index 71161f477c..e4be861716 100644\n> --- a/include/hw/hyperv/hvgdk.h\n> +++ b/include/hw/hyperv/hvgdk.h\n> @@ -9,6 +9,8 @@\n> #ifndef HW_HYPERV_HVGDK_H\n> #define HW_HYPERV_HVGDK_H\n> \n> +#include \"hvgdk_mini.h\"\n> +\n> #define HVGDK_H_VERSION (25125)\n> \n> enum hv_unimplemented_msr_action {\n> diff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h\n> index 41af743847..4a3b543893 100644\n> --- a/include/hw/hyperv/hvhdk.h\n> +++ b/include/hw/hyperv/hvhdk.h\n> @@ -9,7 +9,11 @@\n> #ifndef HW_HYPERV_HVHDK_H\n> #define HW_HYPERV_HVHDK_H\n> \n> +#include \"hvgdk.h\"\n> +#include \"hvhdk_mini.h\"\n> +\n> #define HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS 1\n> +#define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT 7\n> \n> struct hv_input_set_partition_property {\n> uint64_t partition_id;\n> @@ -246,4 +250,105 @@ typedef struct hv_input_register_intercept_result {\n> union hv_register_intercept_result_parameters parameters;\n> } QEMU_PACKED hv_input_register_intercept_result;\n> \n> +/* Flags for dirty mask of hv_vp_register_page */\n> +enum hv_x64_register_class_type {\n> + HV_X64_REGISTER_CLASS_GENERAL = 0,\n> + HV_X64_REGISTER_CLASS_IP = 1,\n> + HV_X64_REGISTER_CLASS_XMM = 2,\n> + HV_X64_REGISTER_CLASS_SEGMENT = 3,\n> + HV_X64_REGISTER_CLASS_FLAGS = 4,\n> +};\n> +\n> +union hv_vp_register_page_interrupt_vectors {\n> + uint64_t as_uint64;\n> + struct {\n> + uint8_t vector_count;\n> + uint8_t vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT];\n> + };\n> +};\n> +\n> +struct hv_vp_register_page {\n> + uint16_t version;\n> + uint8_t isvalid;\n> + uint8_t rsvdz;\n> + uint32_t dirty;\n> +\n> + union {\n> + struct {\n> + /* General purpose registers (HV_X64_REGISTER_CLASS_GENERAL) */\n> + union {\n> + struct {\n> + uint64_t rax;\n> + uint64_t rcx;\n> + uint64_t rdx;\n> + uint64_t rbx;\n> + uint64_t rsp;\n> + uint64_t rbp;\n> + uint64_t rsi;\n> + uint64_t rdi;\n> + uint64_t r8;\n> + uint64_t r9;\n> + uint64_t r10;\n> + uint64_t r11;\n> + uint64_t r12;\n> + uint64_t r13;\n> + uint64_t r14;\n> + uint64_t r15;\n> + } QEMU_PACKED;\n> +\n> + uint64_t gp_registers[16];\n> + };\n> + /* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */\n> + uint64_t rip;\n> + /* Flags (HV_X64_REGISTER_CLASS_FLAGS) */\n> + uint64_t rflags;\n> + } QEMU_PACKED;\n> +\n> + uint64_t registers[18];\n> + };\n> + uint8_t reserved[8];\n> + /* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */\n> + union {\n> + struct {\n> + struct hv_u128 xmm0;\n> + struct hv_u128 xmm1;\n> + struct hv_u128 xmm2;\n> + struct hv_u128 xmm3;\n> + struct hv_u128 xmm4;\n> + struct hv_u128 xmm5;\n> + } QEMU_PACKED;\n> +\n> + struct hv_u128 xmm_registers[6];\n> + };\n> + /* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */\n> + union {\n> + struct {\n> + struct hv_x64_segment_register es;\n> + struct hv_x64_segment_register cs;\n> + struct hv_x64_segment_register ss;\n> + struct hv_x64_segment_register ds;\n> + struct hv_x64_segment_register fs;\n> + struct hv_x64_segment_register gs;\n> + } QEMU_PACKED;\n> +\n> + struct hv_x64_segment_register segment_registers[6];\n> + };\n> + /* Misc. control registers (cannot be set via this interface) */\n> + uint64_t cr0;\n> + uint64_t cr3;\n> + uint64_t cr4;\n> + uint64_t cr8;\n> + uint64_t efer;\n> + uint64_t dr7;\n> + union hv_x64_pending_interruption_register pending_interruption;\n> + union hv_x64_interrupt_state_register interrupt_state;\n> + uint64_t instruction_emulation_hints;\n> + uint64_t xfem;\n> +\n> + uint8_t reserved1[0x100];\n> +\n> + /* Interrupts injected as part of HvCallDispatchVp. */\n> + union hv_vp_register_page_interrupt_vectors interrupt_vectors;\n> +} QEMU_PACKED;\n> +\n> #endif /* HW_HYPERV_HVHDK_H */\n> -- \n> 2.53.0\n\nReviewed-by: Magnus Kulke ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 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","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3687791,"web_url":"http://patchwork.ozlabs.org/comment/3687791/","msgid":"<20260507-furry-pheasant-of-wealth-c3b0a6@anirudhrb>","list_archive_url":null,"date":"2026-05-07T13:15:06","subject":"Re: [PATCH v2 3/7] include/hw/hyperv: add hv_vp_register_page struct\n definition","submitter":{"id":78917,"url":"http://patchwork.ozlabs.org/api/people/78917/","name":"Anirudh Rayabharam","email":"anirudh@anirudhrb.com"},"content":"On Tue, May 05, 2026 at 09:50:24PM +0300, Doru Blânzeanu wrote:\n> Define the `hv_vp_register_page` structure that the linux kernel uses\n> to allow access to vcpu registers.\n> \n> This structure is going to be used in later patches to access vcpu\n> registers.\n> \n> Signed-off-by: Doru Blânzeanu \n> ---\n> include/hw/hyperv/hvgdk.h | 2 +\n> include/hw/hyperv/hvhdk.h | 105 ++++++++++++++++++++++++++++++++++++++\n> 2 files changed, 107 insertions(+)\n\nReviewed-by: Anirudh Rayabharam (Microsoft) ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=anirudhrb.com header.i=anirudh@anirudhrb.com\n header.a=rsa-sha256 header.s=zoho header.b=y0T/A/UY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate 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