[{"id":3686686,"web_url":"http://patchwork.ozlabs.org/comment/3686686/","msgid":"<20260505202629.352A9C2BCB4@smtp.kernel.org>","list_archive_url":null,"date":"2026-05-05T20:26:28","subject":"Re: [PATCH v17 01/11] PCI/AER: Introduce AER-CXL Kfifo","submitter":{"id":93311,"url":"http://patchwork.ozlabs.org/api/people/93311/","name":null,"email":"sashiko-bot@kernel.org"},"content":"Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:\n- [High] Early exit in `for_each_cxl_proto_err()` strands remaining kfifo items and leaks `pci_dev` references.\n--\n\ncommit fc9ac9cc58a6a77c19c9c8d750f3b41f9490529e\nAuthor: Terry Bowman \n\nPCI/AER: Introduce AER-CXL Kfifo\n\nThis commit introduces a kfifo work queue to be used by the AER and CXL\ndrivers for CXL protocol error handling. It adds registration functions and\na cxl_forward_error() function to queue the errors with their associated\nPCI device.\n\n> diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c\n> new file mode 100644\n> index 0000000000000..c0fea2c2b9bc6\n> --- /dev/null\n> +++ b/drivers/pci/pcie/aer_cxl_vh.c\n\n[ ... ]\n\n> +int for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,\n> +\t\t\t cxl_proto_err_fn_t fn)\n> +{\n> +\tint rc;\n> +\n> +\tguard(rwsem_read)(&cxl_proto_err_kfifo.rwsem);\n> +\twhile (kfifo_get(&cxl_proto_err_kfifo.fifo, wd)) {\n> +\t\trc = fn(wd);\n> +\t\tpci_dev_put(wd->pdev);\n> +\t\tif (rc)\n> +\t\t\treturn rc;\n\nIf the consumer callback fn() returns an error, does this early return\nstrand the remaining items in the kfifo?\n\nBecause cxl_forward_error() takes a pci_dev reference for each enqueued\nitem, it looks like these stranded items might leak their pci_dev references\nand prevent clean unbinding or hot-unplug until a new error triggers the\nqueue again.\n\n> +\t}\n> +\n> +\treturn 0;\n> +}","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=KoWunV7e;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1778012789;\n\tbh=CQZeqQJm0IT4vT4vf9BZ4VhHtWv6+YgC76t9f/5ATjA=;\n\th=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From;\n\tb=KoWunV7epQvN2uJaEMF6cw/jhowQ1rs450X7/ITsVzd5pF7HbH+5nfKkKq6pxthq+\n\t Q0N0JY7pk1wRbvCa+qBScp9KEn20Puj3slyTYWnI5wzndOtNikjLdOIPopixGSpifN\n\t MqP3L5pMTWJN/Is5EbDbNl6uAuKhEs6FSZU487wOc/J+71boMg+rRxadBujj0UWen5\n\t zG8HOUbzldRPEI/4zKODmXOlO+d5ctIHY5flBRdtSP6gOTMY2aEKqh3AyuQeGFW+yb\n\t zG5sNtEJ86J4xEneDLwBD4ZH9z2jlVdf55EBFl0rrN+YFaoYCaO9x6SN+52fzwJuo7\n\t jdzh3y2PnuMsg==","From":"sashiko-bot@kernel.org","Subject":"Re: [PATCH v17 01/11] PCI/AER: Introduce AER-CXL Kfifo","Reply-To":"sashiko@lists.linux.dev","To":"\"Terry Bowman\" ","Cc":"linux-pci@vger.kernel.org","In-Reply-To":"<20260505173029.2718246-2-terry.bowman@amd.com>","References":"<20260505173029.2718246-2-terry.bowman@amd.com>","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable","Date":"Tue, 05 May 2026 20:26:28 +0000","Message-Id":"<20260505202629.352A9C2BCB4@smtp.kernel.org>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""}},{"id":3686708,"web_url":"http://patchwork.ozlabs.org/comment/3686708/","msgid":"<3220622a-9241-450c-aedf-d80211eaf561@intel.com>","list_archive_url":null,"date":"2026-05-05T21:17:28","subject":"Re: [PATCH v17 01/11] PCI/AER: Introduce AER-CXL Kfifo","submitter":{"id":13225,"url":"http://patchwork.ozlabs.org/api/people/13225/","name":"Dave Jiang","email":"dave.jiang@intel.com"},"content":"On 5/5/26 10:30 AM, Terry Bowman wrote:\n> CXL virtual hierarchy (VH) native RAS handling for CXL Port devices will be\n> added soon. This requires a notification mechanism for the AER driver to\n> share the AER interrupt with the CXL driver. The CXL drivers use the\n> notification to handle and log the CXL RAS errors.\n> \n> Note, 'CXL protocol error' terminology refers to CXL VH and not CXL RCH\n> errors unless specifically noted going forward.\n> \n> Introduce a new file in the AER driver to handle the CXL protocol\n> errors: pci/pcie/aer_cxl_vh.c.\n> \n> Add a kfifo work queue to be used by the AER and CXL drivers. Multiple\n> AER IRQ worker threads can be running and enqueueing concurrently, so\n> include write path synchronization. Pack the kfifo, the spinlock, the\n> rwsem, and the work pointer into a single structure. Initialize the\n> kfifo with INIT_KFIFO() from a subsys_initcall so its mask, esize and\n> data fields are valid before any producer or consumer runs.\n> \n> Add CXL work queue handler registration functions in the AER driver.\n> Export them so the CXL driver can assign or clear the work handler.\n> \n> Introduce 'struct cxl_proto_err_work_data' to serve as the kfifo work\n> data. It contains a reference to the PCI error source device and the\n> error severity. The cxl_core driver uses this when dequeuing the work.\n> \n> Introduce cxl_forward_error() to add a given CXL protocol error to a\n> work structure and push it onto the AER-CXL kfifo. This function takes\n> a pci_dev_get() on the source device. The kfifo consumer is responsible\n> for the matching pci_dev_put() after dequeue. On enqueue failure\n> cxl_forward_error() does the put itself.\n> \n> Synchronize accesses to the work function pointer during registration,\n> deregistration, enqueue, and dequeue.\n> \n> handle_error_source() is intentionally not changed here. The is_cxl_error()\n> switch that routes errors to cxl_forward_error() is added in a later patch\n> together with the kfifo consumer registration. This way the producer and\n> consumer land in the same commit, so CXL errors are not silently dropped\n> during bisect.\n> \n> Also add MAINTAINERS entries for both drivers/pci/pcie/aer_cxl_vh.c\n> (new in this patch) and drivers/pci/pcie/aer_cxl_rch.c (already in tree\n> but previously unlisted) under the existing CXL entry. This way the CXL\n> maintainers are CC'd on changes to the AER-CXL bridging code.\n> \n> Co-developed-by: Dan Williams \n> Signed-off-by: Dan Williams \n> Signed-off-by: Terry Bowman \n\nReviewed-by: Dave Jiang \n\n\n> \n> ---\n> \n> Changes in v16->v17:\n> - Reword \"kfifo semaphore\" to \"kfifo spinlock\" to match fifo_lock.\n> - Defer the handle_error_source() is_cxl_error() switch to the patch that\n> registers the kfifo consumer to keep each commit bisect-safe.\n> - Rename rwsema to rwsem\n> - Change CPER exports to use EXPORT_SYMBOL_FOR_MODULES.\n> - Add work cancel function.\n> - Replace kfifo_put() with kfifo_in_spinlocked() for multiple producers\n> - Add fifo_lock spinlock for concurrent producer serialisation\n> - Initialize the embedded kfifo with INIT_KFIFO() in a subsys_initcall so\n> kfifo->mask, ->esize and ->data are set before first use.\n> - Clear PCI_ERR_COR_STATUS in cxl_forward_error() before enqueue so the\n> device is acked for correctable events even when the consumer drops the\n> event. Uncorrectable status is left for cxl_do_recovery() to clear after\n> recovery completes, mirroring the AER core convention.\n> - WARN on double-registration in cxl_register_proto_err_work() to make an\n> unintended second consumer visible at runtime.\n> - Add direct rwsem.h, cleanup.h and workqueue.h includes for symbols used\n> in aer_cxl_vh.c\n> - Add MAINTAINERS entries for drivers/pci/pcie/aer_cxl_*.c\n> - Update message\n> \n> Changes in v15->v16:\n> - Add pci_dev_put() and comment in pci_dev_get() (Dan)\n> - /rw_sema/rwsema/ (Dan)\n> - Split validation checks in cxl_forward_error() to allow\n> for meaningful reason in log (Terry)\n> - Shorten commit title to remove wordiness (Terry)\n> - Remove bitfield.h include, unnecessary. (Terry)\n> \n> Changes in v14->v15:\n> - Moved pci_dev_get() call to this patch (Dave)\n> \n> Changes in v13 -> v14:\n> - Replaced workqueue_types.h include with 'struct work_struct'\n> predeclaration (Bjorn)\n> - Update error message (Bjorn)\n> - Reordered 'struct cxl_proto_err_work_data' (Bjorn)\n> - Remove export of cxl_error_is_native() here (Bjorn)\n> \n> Changes in v12->v13:\n> - Added Dave Jiang's review-by\n> - Update error message (Ben)\n> \n> Changes in v11->v12:\n> - None\n> ---\n> MAINTAINERS | 2 +\n> drivers/pci/pcie/Makefile | 1 +\n> drivers/pci/pcie/aer.c | 10 ---\n> drivers/pci/pcie/aer_cxl_vh.c | 142 ++++++++++++++++++++++++++++++++++\n> drivers/pci/pcie/portdrv.h | 4 +\n> include/linux/aer.h | 28 +++++++\n> 6 files changed, 177 insertions(+), 10 deletions(-)\n> create mode 100644 drivers/pci/pcie/aer_cxl_vh.c\n> \n> diff --git a/MAINTAINERS b/MAINTAINERS\n> index 882214b0e7db..93d4e43bb90d 100644\n> --- a/MAINTAINERS\n> +++ b/MAINTAINERS\n> @@ -6433,6 +6433,8 @@ S:\tMaintained\n> F:\tDocumentation/driver-api/cxl\n> F:\tDocumentation/userspace-api/fwctl/fwctl-cxl.rst\n> F:\tdrivers/cxl/\n> +F:\tdrivers/pci/pcie/aer_cxl_rch.c\n> +F:\tdrivers/pci/pcie/aer_cxl_vh.c\n> F:\tinclude/cxl/\n> F:\tinclude/uapi/linux/cxl_mem.h\n> F:\ttools/testing/cxl/\n> diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile\n> index b0b43a18c304..62d3d3c69a5d 100644\n> --- a/drivers/pci/pcie/Makefile\n> +++ b/drivers/pci/pcie/Makefile\n> @@ -9,6 +9,7 @@ obj-$(CONFIG_PCIEPORTBUS)\t+= pcieportdrv.o bwctrl.o\n> obj-y\t\t\t\t+= aspm.o\n> obj-$(CONFIG_PCIEAER)\t\t+= aer.o err.o tlp.o\n> obj-$(CONFIG_CXL_RAS)\t\t+= aer_cxl_rch.o\n> +obj-$(CONFIG_CXL_RAS)\t\t+= aer_cxl_vh.o\n> obj-$(CONFIG_PCIEAER_INJECT)\t+= aer_inject.o\n> obj-$(CONFIG_PCIE_PME)\t\t+= pme.o\n> obj-$(CONFIG_PCIE_DPC)\t\t+= dpc.o\n> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c\n> index c4fd9c0b2a54..c5bce25df51c 100644\n> --- a/drivers/pci/pcie/aer.c\n> +++ b/drivers/pci/pcie/aer.c\n> @@ -1150,16 +1150,6 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)\n> */\n> EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, \"cxl_core\");\n> \n> -#ifdef CONFIG_CXL_RAS\n> -bool is_aer_internal_error(struct aer_err_info *info)\n> -{\n> -\tif (info->severity == AER_CORRECTABLE)\n> -\t\treturn info->status & PCI_ERR_COR_INTERNAL;\n> -\n> -\treturn info->status & PCI_ERR_UNC_INTN;\n> -}\n> -#endif\n> -\n> /**\n> * pci_aer_handle_error - handle logging error into an event log\n> * @dev: pointer to pci_dev data structure of error source device\n> diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c\n> new file mode 100644\n> index 000000000000..c0fea2c2b9bc\n> --- /dev/null\n> +++ b/drivers/pci/pcie/aer_cxl_vh.c\n> @@ -0,0 +1,142 @@\n> +// SPDX-License-Identifier: GPL-2.0-only\n> +/* Copyright(c) 2026 AMD Corporation. All rights reserved. */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \"../pci.h\"\n> +#include \"portdrv.h\"\n> +\n> +#define CXL_ERROR_SOURCES_MAX 128\n> +\n> +struct cxl_proto_err_kfifo {\n> +\tstruct work_struct *work;\n> +\tstruct rw_semaphore rwsem;\n> +\tspinlock_t fifo_lock;\n> +\tDECLARE_KFIFO(fifo, struct cxl_proto_err_work_data,\n> +\t\t CXL_ERROR_SOURCES_MAX);\n> +};\n> +\n> +static struct cxl_proto_err_kfifo cxl_proto_err_kfifo = {\n> +\t.rwsem = __RWSEM_INITIALIZER(cxl_proto_err_kfifo.rwsem),\n> +\t.fifo_lock = __SPIN_LOCK_UNLOCKED(cxl_proto_err_kfifo.fifo_lock),\n> +};\n> +\n> +static int __init cxl_proto_err_kfifo_init(void)\n> +{\n> +\tINIT_KFIFO(cxl_proto_err_kfifo.fifo);\n> +\treturn 0;\n> +}\n> +subsys_initcall(cxl_proto_err_kfifo_init);\n> +\n> +bool is_aer_internal_error(struct aer_err_info *info)\n> +{\n> +\tif (info->severity == AER_CORRECTABLE)\n> +\t\treturn info->status & PCI_ERR_COR_INTERNAL;\n> +\n> +\treturn info->status & PCI_ERR_UNC_INTN;\n> +}\n> +\n> +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info)\n> +{\n> +\tif (!info || !info->is_cxl)\n> +\t\treturn false;\n> +\n> +\tif (pci_pcie_type(pdev) != PCI_EXP_TYPE_ENDPOINT)\n> +\t\treturn false;\n> +\n> +\treturn is_aer_internal_error(info);\n> +}\n> +\n> +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info)\n> +{\n> +\tstruct cxl_proto_err_work_data wd = {\n> +\t\t.severity = info->severity,\n> +\t\t.pdev = pdev,\n> +\t};\n> +\n> +\tif (info->severity == AER_CORRECTABLE)\n> +\t\tpci_write_config_dword(pdev, pdev->aer_cap + PCI_ERR_COR_STATUS,\n> +\t\t\t\t info->status);\n> +\n> +\tguard(rwsem_read)(&cxl_proto_err_kfifo.rwsem);\n> +\n> +\tif (!cxl_proto_err_kfifo.work) {\n> +\t\tdev_err_ratelimited(&pdev->dev, \"AER-CXL kfifo reader not registered\\n\");\n> +\t\treturn;\n> +\t}\n> +\n> +\t/*\n> +\t * Reference discipline: the AER caller (handle_error_source())\n> +\t * holds a ref on @pdev for the duration of this call and releases\n> +\t * it on return. Take a fresh ref here so the pdev stays live while\n> +\t * queued in the kfifo; the consumer (for_each_cxl_proto_err())\n> +\t * drops that ref after handling. On enqueue failure below, drop\n> +\t * the ref we just took to avoid a leak.\n> +\t */\n> +\tpci_dev_get(pdev);\n> +\n> +\t/* Serialize concurrent kfifo writers: multiple AER threaded IRQs */\n> +\tif (!kfifo_in_spinlocked(&cxl_proto_err_kfifo.fifo, &wd, 1,\n> +\t\t\t\t &cxl_proto_err_kfifo.fifo_lock)) {\n> +\t\tdev_err_ratelimited(&pdev->dev, \"AER-CXL kfifo add failed\\n\");\n> +\t\tpci_dev_put(pdev);\n> +\t\treturn;\n> +\t}\n> +\n> +\tschedule_work(cxl_proto_err_kfifo.work);\n> +}\n> +\n> +void cxl_register_proto_err_work(struct work_struct *work)\n> +{\n> +\tguard(rwsem_write)(&cxl_proto_err_kfifo.rwsem);\n> +\tWARN_ONCE(cxl_proto_err_kfifo.work,\n> +\t\t \"AER-CXL kfifo consumer already registered\\n\");\n> +\tcxl_proto_err_kfifo.work = work;\n> +}\n> +EXPORT_SYMBOL_FOR_MODULES(cxl_register_proto_err_work, \"cxl_core\");\n> +\n> +static struct work_struct *cancel_cxl_proto_err(void)\n> +{\n> +\tstruct work_struct *work;\n> +\tstruct cxl_proto_err_work_data wd;\n> +\n> +\tguard(rwsem_write)(&cxl_proto_err_kfifo.rwsem);\n> +\twork = cxl_proto_err_kfifo.work;\n> +\tcxl_proto_err_kfifo.work = NULL;\n> +\twhile (kfifo_get(&cxl_proto_err_kfifo.fifo, &wd)) {\n> +\t\tdev_err_ratelimited(&wd.pdev->dev,\n> +\t\t\t\t \"AER-CXL error report canceled\\n\");\n> +\t\tpci_dev_put(wd.pdev);\n> +\t}\n> +\treturn work;\n> +}\n> +\n> +void cxl_unregister_proto_err_work(void)\n> +{\n> +\tstruct work_struct *work = cancel_cxl_proto_err();\n> +\n> +\tif (work)\n> +\t\tcancel_work_sync(work);\n> +}\n> +EXPORT_SYMBOL_FOR_MODULES(cxl_unregister_proto_err_work, \"cxl_core\");\n> +\n> +int for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,\n> +\t\t\t cxl_proto_err_fn_t fn)\n> +{\n> +\tint rc;\n> +\n> +\tguard(rwsem_read)(&cxl_proto_err_kfifo.rwsem);\n> +\twhile (kfifo_get(&cxl_proto_err_kfifo.fifo, wd)) {\n> +\t\trc = fn(wd);\n> +\t\tpci_dev_put(wd->pdev);\n> +\t\tif (rc)\n> +\t\t\treturn rc;\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +EXPORT_SYMBOL_FOR_MODULES(for_each_cxl_proto_err, \"cxl_core\");\n> diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h\n> index cc58bf2f2c84..66a6b8099c96 100644\n> --- a/drivers/pci/pcie/portdrv.h\n> +++ b/drivers/pci/pcie/portdrv.h\n> @@ -130,9 +130,13 @@ struct aer_err_info;\n> bool is_aer_internal_error(struct aer_err_info *info);\n> void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info);\n> void cxl_rch_enable_rcec(struct pci_dev *rcec);\n> +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info);\n> +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info);\n> #else\n> static inline bool is_aer_internal_error(struct aer_err_info *info) { return false; }\n> static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { }\n> static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { }\n> +static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) { return false; }\n> +static inline void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info) { }\n> #endif /* CONFIG_CXL_RAS */\n> #endif /* _PORTDRV_H_ */\n> diff --git a/include/linux/aer.h b/include/linux/aer.h\n> index df0f5c382286..78841cf4268c 100644\n> --- a/include/linux/aer.h\n> +++ b/include/linux/aer.h\n> @@ -25,6 +25,7 @@\n> #define PCIE_STD_MAX_TLP_HEADERLOG\t(PCIE_STD_NUM_TLP_HEADERLOG + 10)\n> \n> struct pci_dev;\n> +struct work_struct;\n> \n> struct pcie_tlp_log {\n> \tunion {\n> @@ -53,6 +54,18 @@ struct aer_capability_regs {\n> \tu16 uncor_err_source;\n> };\n> \n> +/**\n> + * struct cxl_proto_err_work_data - Error information used in CXL error handling\n> + * @pdev: PCI device detecting the error\n> + * @severity: AER severity\n> + */\n> +struct cxl_proto_err_work_data {\n> +\tstruct pci_dev *pdev;\n> +\tint severity;\n> +};\n> +\n> +typedef int (*cxl_proto_err_fn_t)(struct cxl_proto_err_work_data *wd);\n> +\n> #if defined(CONFIG_PCIEAER)\n> int pci_aer_clear_nonfatal_status(struct pci_dev *dev);\n> int pcie_aer_is_native(struct pci_dev *dev);\n> @@ -66,6 +79,21 @@ static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }\n> static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }\n> #endif\n> \n> +#ifdef CONFIG_CXL_RAS\n> +void cxl_register_proto_err_work(struct work_struct *work);\n> +int for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,\n> +\t\t\t cxl_proto_err_fn_t fn);\n> +void cxl_unregister_proto_err_work(void);\n> +#else\n> +static inline void cxl_register_proto_err_work(struct work_struct *work) { }\n> +static inline int for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,\n> +\t\t\t\t\t cxl_proto_err_fn_t fn)\n> +{\n> +\treturn 0;\n> +}\n> +static inline void cxl_unregister_proto_err_work(void) { }\n> +#endif\n> +\n> void pci_print_aer(struct pci_dev *dev, int aer_severity,\n> \t\t struct aer_capability_regs *aer);\n> int cper_severity_to_aer(int cper_severity);","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=dksw/bYK;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; 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a=\"90274781\"","E=Sophos;i=\"6.23,218,1770624000\";\n d=\"scan'208\";a=\"90274781\"","E=Sophos;i=\"6.23,218,1770624000\";\n d=\"scan'208\";a=\"232798261\""],"X-ExtLoop1":"1","Message-ID":"<3220622a-9241-450c-aedf-d80211eaf561@intel.com>","Date":"Tue, 5 May 2026 14:17:28 -0700","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH v17 01/11] PCI/AER: Introduce AER-CXL Kfifo","To":"Terry Bowman , dave@stgolabs.net, jic23@kernel.org,\n alison.schofield@intel.com, djbw@kernel.org, bhelgaas@google.com,\n shiju.jose@huawei.com, ming.li@zohomail.com,\n Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,\n dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,\n lukas@wunner.de, Benjamin.Cheatham@amd.com,\n sathyanarayanan.kuppuswamy@linux.intel.com, vishal.l.verma@intel.com,\n alucerop@amd.com, ira.weiny@intel.com, corbet@lwn.net, rafael@kernel.org,\n xueshuai@linux.alibaba.com, linux-cxl@vger.kernel.org","Cc":"linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n <20260505173029.2718246-2-terry.bowman@amd.com>","Content-Language":"en-US","From":"Dave Jiang ","In-Reply-To":"<20260505173029.2718246-2-terry.bowman@amd.com>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit"}},{"id":3687976,"web_url":"http://patchwork.ozlabs.org/comment/3687976/","msgid":"<20260507185303.329cf964@jic23-huawei>","list_archive_url":null,"date":"2026-05-07T17:53:03","subject":"Re: [PATCH v17 01/11] PCI/AER: Introduce AER-CXL Kfifo","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Tue, 5 May 2026 12:30:19 -0500\nTerry Bowman wrote:\n\n> CXL virtual hierarchy (VH) native RAS handling for CXL Port devices will be\n> added soon. This requires a notification mechanism for the AER driver to\n> share the AER interrupt with the CXL driver. The CXL drivers use the\n> notification to handle and log the CXL RAS errors.\n> \n> Note, 'CXL protocol error' terminology refers to CXL VH and not CXL RCH\n> errors unless specifically noted going forward.\n> \n> Introduce a new file in the AER driver to handle the CXL protocol\n> errors: pci/pcie/aer_cxl_vh.c.\n> \n> Add a kfifo work queue to be used by the AER and CXL drivers. Multiple\n> AER IRQ worker threads can be running and enqueueing concurrently, so\n> include write path synchronization. Pack the kfifo, the spinlock, the\n> rwsem, and the work pointer into a single structure. Initialize the\n> kfifo with INIT_KFIFO() from a subsys_initcall so its mask, esize and\n> data fields are valid before any producer or consumer runs.\n> \n> Add CXL work queue handler registration functions in the AER driver.\n> Export them so the CXL driver can assign or clear the work handler.\n> \n> Introduce 'struct cxl_proto_err_work_data' to serve as the kfifo work\n> data. It contains a reference to the PCI error source device and the\n> error severity. The cxl_core driver uses this when dequeuing the work.\n> \n> Introduce cxl_forward_error() to add a given CXL protocol error to a\n> work structure and push it onto the AER-CXL kfifo. This function takes\n> a pci_dev_get() on the source device. The kfifo consumer is responsible\n> for the matching pci_dev_put() after dequeue. On enqueue failure\n> cxl_forward_error() does the put itself.\n> \n> Synchronize accesses to the work function pointer during registration,\n> deregistration, enqueue, and dequeue.\n> \n> handle_error_source() is intentionally not changed here. The is_cxl_error()\n> switch that routes errors to cxl_forward_error() is added in a later patch\n> together with the kfifo consumer registration. This way the producer and\n> consumer land in the same commit, so CXL errors are not silently dropped\n> during bisect.\n> \n> Also add MAINTAINERS entries for both drivers/pci/pcie/aer_cxl_vh.c\n> (new in this patch) and drivers/pci/pcie/aer_cxl_rch.c (already in tree\n> but previously unlisted) under the existing CXL entry. This way the CXL\n> maintainers are CC'd on changes to the AER-CXL bridging code.\n> \n> Co-developed-by: Dan Williams \n> Signed-off-by: Dan Williams \n> Signed-off-by: Terry Bowman \n\nSashiko did have one comment on what happens if there are multiple things\nin the kfifo and fn fails. At that point I think we are in the all\nbets are off corner and stranding a driver is fine, but open to other opinions!\n\nhttps://sashiko.dev/#/patchset/20260505173029.2718246-1-terry.bowman%40amd.com\n\nSo with that in mind\n\nReviewed-by: Jonathan Cameron \n\n> diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c\n> new file mode 100644\n> index 000000000000..c0fea2c2b9bc\n> --- /dev/null\n> +++ b/drivers/pci/pcie/aer_cxl_vh.c\n\n\n> +int for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,\n> +\t\t\t cxl_proto_err_fn_t fn)\n> +{\n> +\tint rc;\n> +\n> +\tguard(rwsem_read)(&cxl_proto_err_kfifo.rwsem);\n> +\twhile (kfifo_get(&cxl_proto_err_kfifo.fifo, wd)) {\n> +\t\trc = fn(wd);\n> +\t\tpci_dev_put(wd->pdev);\n> +\t\tif (rc)\n> +\t\t\treturn rc;\nThis is where Sashiko complains. Specifically:\n\"If the consumer callback fn() returns an error, does this early return\nstrand the remaining items in the kfifo?\nBecause cxl_forward_error() takes a pci_dev reference for each enqueued\nitem, it looks like these stranded items might leak their pci_dev references\nand prevent clean unbinding or hot-unplug until a new error triggers the\nqueue again.\"\n\nI'd go with indeed it does, but there is no right thing to do here. I guess\nwe could flush the kfifo and call pci_dev_put() on each of them, but that's horrible.\nWould basically mean calling the same stuff you have for cancelling outstanding\nentrees on exit().\n\n\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +EXPORT_SYMBOL_FOR_MODULES(for_each_cxl_proto_err, \"cxl_core\");","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=FV1ZCd+7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54110-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"FV1ZCd+7\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBKgY3qxkz1yCg\n\tfor ; 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x86_64-pc-linux-gnu)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit"}},{"id":3687986,"web_url":"http://patchwork.ozlabs.org/comment/3687986/","msgid":"","list_archive_url":null,"date":"2026-05-07T18:26:51","subject":"Re: [PATCH v17 01/11] PCI/AER: Introduce AER-CXL Kfifo","submitter":{"id":82124,"url":"http://patchwork.ozlabs.org/api/people/82124/","name":"Bowman, Terry","email":"Terry.Bowman@amd.com"},"content":"On 5/7/2026 12:53 PM, Jonathan Cameron wrote:\n> On Tue, 5 May 2026 12:30:19 -0500\n> Terry Bowman wrote:\n> \n>> CXL virtual hierarchy (VH) native RAS handling for CXL Port devices will be\n>> added soon. This requires a notification mechanism for the AER driver to\n>> share the AER interrupt with the CXL driver. The CXL drivers use the\n>> notification to handle and log the CXL RAS errors.\n>>\n>> Note, 'CXL protocol error' terminology refers to CXL VH and not CXL RCH\n>> errors unless specifically noted going forward.\n>>\n>> Introduce a new file in the AER driver to handle the CXL protocol\n>> errors: pci/pcie/aer_cxl_vh.c.\n>>\n>> Add a kfifo work queue to be used by the AER and CXL drivers. Multiple\n>> AER IRQ worker threads can be running and enqueueing concurrently, so\n>> include write path synchronization. Pack the kfifo, the spinlock, the\n>> rwsem, and the work pointer into a single structure. Initialize the\n>> kfifo with INIT_KFIFO() from a subsys_initcall so its mask, esize and\n>> data fields are valid before any producer or consumer runs.\n>>\n>> Add CXL work queue handler registration functions in the AER driver.\n>> Export them so the CXL driver can assign or clear the work handler.\n>>\n>> Introduce 'struct cxl_proto_err_work_data' to serve as the kfifo work\n>> data. It contains a reference to the PCI error source device and the\n>> error severity. The cxl_core driver uses this when dequeuing the work.\n>>\n>> Introduce cxl_forward_error() to add a given CXL protocol error to a\n>> work structure and push it onto the AER-CXL kfifo. This function takes\n>> a pci_dev_get() on the source device. The kfifo consumer is responsible\n>> for the matching pci_dev_put() after dequeue. On enqueue failure\n>> cxl_forward_error() does the put itself.\n>>\n>> Synchronize accesses to the work function pointer during registration,\n>> deregistration, enqueue, and dequeue.\n>>\n>> handle_error_source() is intentionally not changed here. The is_cxl_error()\n>> switch that routes errors to cxl_forward_error() is added in a later patch\n>> together with the kfifo consumer registration. This way the producer and\n>> consumer land in the same commit, so CXL errors are not silently dropped\n>> during bisect.\n>>\n>> Also add MAINTAINERS entries for both drivers/pci/pcie/aer_cxl_vh.c\n>> (new in this patch) and drivers/pci/pcie/aer_cxl_rch.c (already in tree\n>> but previously unlisted) under the existing CXL entry. This way the CXL\n>> maintainers are CC'd on changes to the AER-CXL bridging code.\n>>\n>> Co-developed-by: Dan Williams \n>> Signed-off-by: Dan Williams \n>> Signed-off-by: Terry Bowman \n> \n> Sashiko did have one comment on what happens if there are multiple things\n> in the kfifo and fn fails. At that point I think we are in the all\n> bets are off corner and stranding a driver is fine, but open to other opinions!\n> \n> https://sashiko.dev/#/patchset/20260505173029.2718246-1-terry.bowman%40amd.com\n> \n> So with that in mind\n> \n> Reviewed-by: Jonathan Cameron \n> \n\nHi Jonathan,\n\nI resolved this for next series by changing __cxl_proto_err_work_fn() to return void \nas the error case was unnecessary and only added complexity. \n\n\n\n>> diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c\n>> new file mode 100644\n>> index 000000000000..c0fea2c2b9bc\n>> --- /dev/null\n>> +++ b/drivers/pci/pcie/aer_cxl_vh.c\n> \n> \n>> +int for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,\n>> +\t\t\t cxl_proto_err_fn_t fn)\n>> +{\n>> +\tint rc;\n>> +\n>> +\tguard(rwsem_read)(&cxl_proto_err_kfifo.rwsem);\n>> +\twhile (kfifo_get(&cxl_proto_err_kfifo.fifo, wd)) {\n>> +\t\trc = fn(wd);\n>> +\t\tpci_dev_put(wd->pdev);\n>> +\t\tif (rc)\n>> +\t\t\treturn rc;\n> This is where Sashiko complains. Specifically:\n> \"If the consumer callback fn() returns an error, does this early return\n> strand the remaining items in the kfifo?\n> Because cxl_forward_error() takes a pci_dev reference for each enqueued\n> item, it looks like these stranded items might leak their pci_dev references\n> and prevent clean unbinding or hot-unplug until a new error triggers the\n> queue again.\"\n> \n> I'd go with indeed it does, but there is no right thing to do here. I guess\n> we could flush the kfifo and call pci_dev_put() on each of them, but that's horrible.\n> Would basically mean calling the same stuff you have for cancelling outstanding\n> entrees on exit().\n> \n> \n\nYes, that is an idea. But, until error discriminator is needed this can return void.\nClearing will be necessary but I think that will fit within the call path.\n\n-Terry\n\n\n>> +\t}\n>> +\n>> +\treturn 0;\n>> +}\n>> +EXPORT_SYMBOL_FOR_MODULES(for_each_cxl_proto_err, \"cxl_core\");","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=FoDrb7w0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54116-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com\n header.b=\"FoDrb7w0\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.93.196.8","smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=amd.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=amd.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=amd.com;"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBLNM2XPYz1yCg\n\tfor ; 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