[{"id":3688055,"web_url":"http://patchwork.ozlabs.org/comment/3688055/","msgid":"","list_archive_url":null,"date":"2026-05-07T21:11:19","subject":"Re: [PATCH v2 1/4] reset: Add reset_reset() and reset_reset_bulk()\n API","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"Hi Michal,\n\nOn 2026-05-05T12:30:28, Michal Simek wrote:\n> reset: Add reset_reset() and reset_reset_bulk() API\n>\n> Add reset_reset() and reset_reset_bulk() functions to the reset\n> controller API. These functions assert and then deassert reset signals\n> in a single call, providing a convenient way to pulse/toggle a reset\n> line.\n>\n> This mimics the Linux kernel's reset_control_reset() and\n> reset_control_bulk_reset() APIs. The new functions are useful for\n> drivers that need to cycle a reset line during initialization or\n> error recovery but with also passing delay parameter.\n>\n> If a driver implements the rst_reset op, it will be called directly\n> with the delay parameter. Otherwise, the reset core performs\n> reset_assert(), optional udelay(), and reset_deassert() as fallback.\n>\n> Signed-off-by: Michal Simek \n>\n> drivers/reset/reset-uclass.c | 34 ++++++++++++++++++++++++++++++++++\n> include/reset-uclass.h | 12 ++++++++++++\n> include/reset.h | 41 +++++++++++++++++++++++++++++++++++++++++\n> 3 files changed, 87 insertions(+)\n\nReviewed-by: Simon Glass \n\noptional nits / thoughts below\n\n> diff --git a/include/reset-uclass.h b/include/reset-uclass.h\n> @@ -76,6 +76,18 @@ struct reset_ops {\n> + /**\n> + * rst_reset - Reset a HW module.\n> + *\n> + * This optional function triggers a reset pulse on the reset line,\n> + * asserting and then deasserting the reset signal. If not implemented,\n> + * the reset core will use rst_assert followed by rst_deassert.\n> + *\n> + * @reset_ctl: The reset signal to pulse.\n> + * @delay_us: Delay in microseconds between assert and deassert.\n> + * @return 0 if OK, or a negative error code.\n> + */\n> + int (*rst_reset)(struct reset_ctl *reset_ctl, ulong delay_us);\n\nPlease document that the core inserts a udelay(delay_us) between\nrst_assert and rst_deassert in the fallback path, and clarify whether\nan rst_reset implementation must honour delay_us or may treat it as a\nhint. Without that, authors don't really know what to do with the\nvalue.\n\n> diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c\n> @@ -225,6 +226,39 @@ int reset_deassert_bulk(struct reset_ctl_bulk *bulk)\n> +int reset_reset_bulk(struct reset_ctl_bulk *bulk, ulong delay_us)\n> +{\n> + int i, ret;\n> +\n> + for (i = 0; i < bulk->count; i++) {\n> + ret = reset_reset(&bulk->resets[i], delay_us);\n> + if (ret < 0)\n> + return ret;\n> + }\n> +\n> + return 0;\n> +}\n\nJust to check - pulsing each reset sequentially means the first\nfinishes its full assert/delay/deassert before the next starts\nasserting. For the cadence_qspi case in 3/4, where multiple OSPI reset\nlines are expected to be asserted together, the previous code did\nassert_bulk() / udelay() / deassert_bulk() so all lines were held low\nsimultaneously. The new behaviour is different. Is that intentional,\nand have you confirmed the cadence controller is happy with it?\n\nRegards,\nSimon","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256\n header.s=google header.b=Yk3/ghaP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=chromium.org","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org\n header.b=\"Yk3/ghaP\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=chromium.org","phobos.denx.de;\n spf=pass smtp.mailfrom=sjg@chromium.org"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBQ0s2mWRz1yJq\n\tfor ; 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Thu, 07 May 2026\n 14:11:33 -0700 (PDT)","MIME-Version":"1.0","References":"\n <2a5fee05be84fa1cb333f3ab3db732311da321cf.1777984225.git.michal.simek@amd.com>","In-Reply-To":"\n <2a5fee05be84fa1cb333f3ab3db732311da321cf.1777984225.git.michal.simek@amd.com>","From":"Simon Glass ","Date":"Thu, 7 May 2026 15:11:19 -0600","X-Gm-Features":"AVHnY4KwC4Ptiov_P7Bk4ZtPtodaElYJ0uAuO1V_i779E-7_2T32R5d7fDbgCto","Message-ID":"\n ","Subject":"Re: [PATCH v2 1/4] reset: Add reset_reset() and reset_reset_bulk()\n API","To":"michal.simek@amd.com","Cc":"u-boot@lists.denx.de, git@amd.com, Simon Glass ","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}}]