[{"id":3687566,"web_url":"http://patchwork.ozlabs.org/comment/3687566/","msgid":"<20260507075959.EC384C2BCC7@smtp.kernel.org>","list_archive_url":null,"date":"2026-05-07T07:59:59","subject":"Re: [PATCH v8 phy-next 10/31] scsi: ufs: exynos: use dedicated API\n for updating PHY bus width","submitter":{"id":93311,"url":"http://patchwork.ozlabs.org/api/people/93311/","name":null,"email":"sashiko-bot@kernel.org"},"content":"Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:\n- [High] In `samsung_ufs_phy_request_bus_width()`, if `samsung_ufs_phy_power_on()` fails, the PHY clocks are left disabled but the core `phy->power_count` remains elevated, causing unbalanced clock disables on teardown.\n- [High] Early return on `phy_request_bus_width()` failure skips PHY power-on, causing fatal hardware bus errors when accessing unpowered PHY registers.\n--\n\ncommit 69b368f4a4a2db532d3c3f014c5fffd55e2658d0\nAuthor: Vladimir Oltean \n\nscsi: ufs: exynos: use dedicated API for updating PHY bus width\n\nThis commit introduces a new dedicated phy_request_bus_width() API to the \nPHY core and updates the Exynos UFS driver to use it instead of hijacking\nphy_set_bus_width() and phy_init(). This update allows the UFS HCD driver\nto update the lane count cleanly without altering the PHY initialization and\npower states unexpectedly.\n\n> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c\n> index ee665f26c2361..b09a35ab6acde 100644\n> --- a/drivers/phy/samsung/phy-samsung-ufs.c\n> +++ b/drivers/phy/samsung/phy-samsung-ufs.c\n[ ... ]\n> @@ -204,6 +203,31 @@ static int samsung_ufs_phy_power_off(struct phy *phy)\n> \treturn 0;\n> }\n> \n> +static int samsung_ufs_phy_request_bus_width(struct phy *phy, int bus_width)\n> +{\n> +\tstruct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);\n> +\tu8 old_lane_cnt = ss_phy->lane_cnt;\n> +\tint err = 0;\n> +\n> +\tif (bus_width != 1 && bus_width != 2)\n> +\t\treturn -EINVAL;\n> +\n> +\tss_phy->lane_cnt = bus_width;\n> +\n> +\tif (phy->init_count)\n> +\t\tsamsung_ufs_phy_init(phy);\n> +\n> +\t/* If the init_count is 0, the power_count should also be 0 */\n> +\tif (phy->power_count) {\n> +\t\tsamsung_ufs_phy_power_off(phy);\n> +\t\terr = samsung_ufs_phy_power_on(phy);\n\nIf samsung_ufs_phy_power_on() fails here, the PHY clocks are left disabled but\nthe core phy->power_count remains elevated because this cycle bypasses the core\nPHY API.\n\nWhen the UFS driver later cleans up and calls phy_power_off(), the PHY core\ninvokes samsung_ufs_phy_power_off() a second time.\n\nWill this second call to samsung_ufs_phy_power_off() attempt to disable already\ndisabled clocks and cause a clock enable count underflow warning?\n\n> +\t\tif (err)\n> +\t\t\tss_phy->lane_cnt = old_lane_cnt;\n> +\t}\n> +\n> +\treturn err;\n> +}\n[ ... ]\n> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c\n> index 77a6c8e44485b..b90876b268db7 100644\n> --- a/drivers/ufs/host/ufs-exynos.c\n> +++ b/drivers/ufs/host/ufs-exynos.c\n[ ... ]\n> @@ -947,30 +1009,11 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs)\n> \t\t\tufs->avail_ln_rx, ufs->avail_ln_tx);\n> \t}\n> \n> -\tphy_set_bus_width(generic_phy, ufs->avail_ln_rx);\n> -\n> -\tif (generic_phy->power_count) {\n> -\t\tphy_power_off(generic_phy);\n> -\t\tphy_exit(generic_phy);\n> -\t}\n> -\n> -\tret = phy_init(generic_phy);\n> -\tif (ret) {\n> -\t\tdev_err(hba->dev, \"%s: phy init failed, ret = %d\\n\",\n> -\t\t\t__func__, ret);\n> -\t\treturn ret;\n> -\t}\n> -\n> -\tret = phy_power_on(generic_phy);\n> +\tret = phy_request_bus_width(generic_phy, ufs->avail_ln_rx);\n> \tif (ret)\n> -\t\tgoto out_exit_phy;\n> -\n> -\treturn 0;\n> -\n> -out_exit_phy:\n> -\tphy_exit(generic_phy);\n> +\t\treturn ret;\n> \n> -\treturn ret;\n> +\treturn exynos_ufs_phy_power_on(ufs);\n> }\n\nIf phy_request_bus_width() fails and returns an error (for example, -EINVAL\nif ufs->avail_ln_rx is 0), this code will return early and skip the call to\nexynos_ufs_phy_power_on().\n\nHowever, looking at exynos_ufs_pre_link() which calls this function:\n\nexynos_ufs_pre_link() {\n...\n\t/* m-phy */\n\texynos_ufs_phy_update_bus_width(ufs);\n\tif (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {\n\t\texynos_ufs_config_phy_time_attr(ufs);\n\t\texynos_ufs_config_phy_cap_attr(ufs);\n\t}\n...\n}\n\nThe return value of exynos_ufs_phy_update_bus_width() is ignored, and\nexynos_ufs_pre_link() proceeds unconditionally to access PHY attributes via\nexynos_ufs_config_phy_time_attr() and exynos_ufs_config_phy_cap_attr().\n\nCan accessing these registers while the PHY power domains and clocks are off\ncause unhandled faults, bus errors, or hardware hangs?","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=R/StLScR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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