[{"id":3687569,"web_url":"http://patchwork.ozlabs.org/comment/3687569/","msgid":"<20260507080002.75B01C2BCC7@smtp.kernel.org>","list_archive_url":null,"date":"2026-05-07T08:00:01","subject":"Re: [PATCH v8 phy-next 12/31] scsi: ufs: qcom: make use of QMP PHY\n dynamic gear switching ability","submitter":{"id":93311,"url":"http://patchwork.ozlabs.org/api/people/93311/","name":null,"email":"sashiko-bot@kernel.org"},"content":"Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:\n- [High] Missing error check on qmp_ufs_power_on() leads to a system crash on unclocked register access.\n- [Medium] Bypassing the PHY framework for power cycling desynchronizes the framework's power state, causing resource double-disables on failure.\n--\n\ncommit f4f0468d1ef7ec1cda5450a4d318d324cf1517f6\nAuthor: Vladimir Oltean \n\nscsi: ufs: qcom: make use of QMP PHY dynamic gear switching ability\n\nThis commit absorbs the PHY power cycling and calibration sequence into\nqmp_ufs_set_mode() to simplify the consumer driver. It updates both the UFS\nHCD consumer and the QMP PHY provider simultaneously to avoid breaking the\npower sequence.\n\n> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c\n> index 771bc7c2ab505..e4e7966eb39a6 100644\n> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c\n> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c\n> @@ -2012,6 +2012,12 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)\n> \tqmp->mode = mode;\n> \tqmp->submode = submode;\n> \n> +\tif (phy->power_count) {\n> +\t\tqmp_ufs_power_off(phy);\n> +\t\tqmp_ufs_power_on(phy);\n\nDoes the return value of qmp_ufs_power_on() need to be checked here?\n\nIf qmp_ufs_power_on() fails, the PHY clocks and regulators will remain\ndisabled.\n\nBecause the error is ignored, execution unconditionally proceeds to\nqmp_ufs_phy_calibrate(), which performs read/modify/write operations on the\nPHY memory-mapped registers. Accessing peripheral registers while their\nclocks are disabled can cause a synchronous external abort and a kernel\npanic.\n\nAdditionally, does calling the internal power routines directly cause issues\nwith the PHY framework state tracking?\n\nBy calling qmp_ufs_power_off() and qmp_ufs_power_on() instead of the public\nphy_power_off() and phy_power_on() APIs, phy->power_count remains unchanged.\n\nIf qmp_ufs_power_on() fails leaving the hardware unpowered, the framework\nwill still believe the PHY is powered on. During error handling or teardown,\nthe core might call phy_power_off(). Would this result in a second call\nto qmp_ufs_power_off() and cause reference count underflow warnings for the\nclocks and regulators?\n\n> +\t\treturn qmp_ufs_phy_calibrate(phy);\n> +\t}\n> +\n> \treturn 0;\n> }","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=tLen/GEi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-54052-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"tLen/GEi\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gB4Rg0hC9z1yCg\n\tfor ; Thu, 07 May 2026 18:00:15 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id 1CBE9300C03C\n\tfor ; Thu, 7 May 2026 08:00:12 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1A083325716;\n\tThu, 7 May 2026 08:00:05 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 82C1D37F754\n\tfor ; Thu, 7 May 2026 08:00:03 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 75B01C2BCC7;\n\tThu, 7 May 2026 08:00:02 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778140803; cv=none;\n b=eVzGUgE6Z4AbBi1JI58Ble5hKpoMQr3mBvo2sUeWqZKO/n/+8hF2++fqms8gzuRn6/3EfUWaUSxPj1DHbWaGJQaU5kihW2+jvOV9vBu2oOyc4JuB5Xs2ncSqPlxZE+SiByxsm8WQCQz+ohdV5bCW4MC4NFdoc0KwdMjhIOD+WGg=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778140803; c=relaxed/simple;\n\tbh=Se8DNUOvARlazVwQdghiZ4bqy4wOyzPNEesapZqAZWE=;\n\th=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date:\n\t Message-Id;\n b=BKeStt7TF+rGWId60s41iflIBhKydWYKhcGNttyBVq+OYZdwyeNXfKV3pbh5z7GGdmbTKBJdOrYQnXFKL5H+OiL3e4HBWUH0i+UVDaeXQRtqajkgbN8siukdIGjuzL3Jd6Kz1rnGtOTnGcu09ZFQjZKptXACM75HFgu//JdaiLs=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=tLen/GEi; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1778140802;\n\tbh=Se8DNUOvARlazVwQdghiZ4bqy4wOyzPNEesapZqAZWE=;\n\th=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From;\n\tb=tLen/GEitFcX9OO6XiB8RDZs60SJY9YCOxLauAzY+hDYkIAUIA1LJgerE4bPtTJeR\n\t hEkNpyLlCwx8ZDcyjG0/ebvGSAsVxtR5Y4zwt2ud2d6QwhYTfgdBb3eQECeNYyzUvs\n\t 3BG756naDgKeUv1xBgUmcEETYtdW8ER8sTJ9IIKYa0yE9z+Lz6Nqk188P/q/rCFPMx\n\t NHockbfAx2GyENCZY2LeLkqYts43W8MnQls0cp8BvwhVi/U+bmpgWcJ1FiXEtyk/gM\n\t T8DuOyCnteGS39UqJ+WWbRfbECwgLjXtsrdspr6Jc6StoIZAma76AgaLa6ULHMGUPy\n\t A0fKRYyzXAtKA==","From":"sashiko-bot@kernel.org","Subject":"Re: [PATCH v8 phy-next 12/31] scsi: ufs: qcom: make use of QMP PHY\n dynamic gear switching ability","Reply-To":"sashiko@lists.linux.dev","To":"\"Vladimir Oltean\" ","Cc":"linux-pci@vger.kernel.org, wsa+renesas@sang-engineering.com","In-Reply-To":"<20260505100523.1922388-13-vladimir.oltean@nxp.com>","References":"<20260505100523.1922388-13-vladimir.oltean@nxp.com>","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable","Date":"Thu, 07 May 2026 08:00:01 +0000","Message-Id":"<20260507080002.75B01C2BCC7@smtp.kernel.org>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""}}]