[{"id":3685434,"web_url":"http://patchwork.ozlabs.org/comment/3685434/","msgid":"<87zf2gtj7l.fsf@googlemail.com>","list_archive_url":null,"date":"2026-05-03T18:57:02","subject":"Re: [to-be-committed][RISC-V][PR rtl-optimization/124766] Simplify\n x + y == y into x == 0","submitter":{"id":4363,"url":"http://patchwork.ozlabs.org/api/people/4363/","name":"Richard Sandiford","email":"rdsandiford@googlemail.com"},"content":"Jeffrey Law writes:\n> So this is derived from S_regmatch in spec2017, so fairly hot.\n>\n>\n>\n> long\n> frob (unsigned short *y, long z)\n> {\n>   long ret = (*y << 2) + z;\n>   if (ret != z)\n>     return 0;\n>   return ret;\n> }\n>\n> It generates this code on riscv:\n>\n>\n>         lhu     a5,0(a0)\n>         sh2add  a5,a5,a1\n>         sub     a1,a1,a5\n>         czero.nez       a0,a5,a1\n>         ret\n>\n> That's not bad, but the sh2add and sub are not actually needed. This may \n> look familiar to a case Daniel was recently discussing, the major \n> difference are the types of the function args which I got wrong the \n> first time I reduced this case.\n>\n> czero instructions check their condition for zero/nonzero status. So we \n> just need to know if a1 has a zero/nonzero value at the czero \n> instruction.  So working backwards\n>\n> a1 = a1 - a5                // sub instruction\n> a1 = a1 - ((a5 << 2) + a1)  // substitute from sh2add\n> a1 = a5 << 2                // a1 terms cancel out\n>\n> So we just need the nonzero state of a5 << 2.  Now since a5 was set by \n> the lhu instruction, the upper 48 bits are already known zero, so \n> critically we know the upper 2 bits are zero. Meaning that we can just \n> test a5 as set by the lhu instruction for zero/nonzero.  The net is we \n> can generate this code instead:\n>\n>         lhu     a0,0(a0)\n>         czero.nez       a0,a1,a0\n>         ret\n>\n>\n> It's a small, but visible instruction count savings and likely a small \n> performance improvement on most designs.\n>\n> So the trick to get there is a small simplify-rtx improvement. We just \n> need to simplify\n> (eq/ne (plus (x) (y)) (y)) ->  (eq/ne (x) (0))\n>\n> And all the right things just happen.  Bootstrapped and regression \n> tested on a variety of native platforms including x86, aarch64, riscv \n> and tested across the various embedded targets in my tester.  I'll wait \n> for the RISC-V pre-commit CI tester to render a verdict before going \n> forward.\n>\n>\n> Jeff\n>\n>\n> diff --git a/gcc/testsuite/gcc.target/riscv/pr124766.c b/gcc/testsuite/gcc.target/riscv/pr124766.c\n> new file mode 100644\n> index 000000000000..b16c31e8a9bd\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.target/riscv/pr124766.c\n> @@ -0,0 +1,17 @@\n> +/* { dg-do compile } */\n> +/* { dg-options \"-march=rv64gcbv_zicond -mabi=lp64d\" { target rv64 } } */\n> +/* { dg-options \"-march=rv32gcbv_zicond -mabi=ilp32\" { target rv32 } } */\n> +/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n> +\n> +long\n> +frob (unsigned short *y, long z)\n> +{\n> + long ret = (*y << 2) + z;\n> + if (ret != z)\n> + return 0;\n> + return ret;\n> +}\n> +\n> +/* { dg-final { scan-assembler-not \"sh2add\" } } */\n> +/* { dg-final { scan-assembler-not \"sub\" } } */\n> +\n> diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc\n> index 50fc51152cab..23de16800065 100644\n> --- a/gcc/simplify-rtx.cc\n> +++ b/gcc/simplify-rtx.cc\n> @@ -6649,6 +6649,14 @@ simplify_context::simplify_relational_operation_1 (rtx_code code,\n> return simplify_gen_relational (code, mode, cmp_mode, x, tem);\n> }\n> \n> + /* (eq/ne (plus (x) (y)) y) simplifies to (eq/ne x 0). */\n> + if ((code == EQ || code == NE)\n> + && op0code == PLUS\n> + && XEXP (op0, 1) == op1\n\nLooks like this would be better as rtx_equal_p, since it applies even\nto y that aren't shared. Also...\n\n> + && (INTEGRAL_MODE_P (cmp_mode) || flag_unsafe_math_optimizations))\n> + return simplify_gen_relational (code, mode, cmp_mode,\n> +\t\t\t\t XEXP (op0, 0), const0_rtx);\n\nif we want to support the non-integral flag_unsafe_math_optimizations case,\nwe'd need to use CONST0_RTX (cmp_mode) instead of const0_rtx.\n\nThanks,\nRichard\n\n> +\n> /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is\n> the same as (zero_extract:SI FOO (const_int 1) BAR). */\n> scalar_int_mode int_mode, int_cmp_mode;","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=googlemail.com header.i=@googlemail.com\n header.a=rsa-sha256 header.s=20251104 header.b=ec9iNk7z;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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charset=utf-8","Content-Transfer-Encoding":"quoted-printable","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3685436,"web_url":"http://patchwork.ozlabs.org/comment/3685436/","msgid":"<87tssotix8.fsf@googlemail.com>","list_archive_url":null,"date":"2026-05-03T19:03:15","subject":"Re: [to-be-committed][RISC-V][PR rtl-optimization/124766] Simplify\n x + y == y into x == 0","submitter":{"id":4363,"url":"http://patchwork.ozlabs.org/api/people/4363/","name":"Richard Sandiford","email":"rdsandiford@googlemail.com"},"content":"Richard Sandiford writes:\n> Jeffrey Law writes:\n>> So this is derived from S_regmatch in spec2017, so fairly hot.\n>>\n>>\n>>\n>> long\n>> frob (unsigned short *y, long z)\n>> {\n>>   long ret = (*y << 2) + z;\n>>   if (ret != z)\n>>     return 0;\n>>   return ret;\n>> }\n>>\n>> It generates this code on riscv:\n>>\n>>\n>>         lhu     a5,0(a0)\n>>         sh2add  a5,a5,a1\n>>         sub     a1,a1,a5\n>>         czero.nez       a0,a5,a1\n>>         ret\n>>\n>> That's not bad, but the sh2add and sub are not actually needed. This may \n>> look familiar to a case Daniel was recently discussing, the major \n>> difference are the types of the function args which I got wrong the \n>> first time I reduced this case.\n>>\n>> czero instructions check their condition for zero/nonzero status. So we \n>> just need to know if a1 has a zero/nonzero value at the czero \n>> instruction.  So working backwards\n>>\n>> a1 = a1 - a5                // sub instruction\n>> a1 = a1 - ((a5 << 2) + a1)  // substitute from sh2add\n>> a1 = a5 << 2                // a1 terms cancel out\n>>\n>> So we just need the nonzero state of a5 << 2.  Now since a5 was set by \n>> the lhu instruction, the upper 48 bits are already known zero, so \n>> critically we know the upper 2 bits are zero. Meaning that we can just \n>> test a5 as set by the lhu instruction for zero/nonzero.  The net is we \n>> can generate this code instead:\n>>\n>>         lhu     a0,0(a0)\n>>         czero.nez       a0,a1,a0\n>>         ret\n>>\n>>\n>> It's a small, but visible instruction count savings and likely a small \n>> performance improvement on most designs.\n>>\n>> So the trick to get there is a small simplify-rtx improvement. We just \n>> need to simplify\n>> (eq/ne (plus (x) (y)) (y)) ->  (eq/ne (x) (0))\n>>\n>> And all the right things just happen.  Bootstrapped and regression \n>> tested on a variety of native platforms including x86, aarch64, riscv \n>> and tested across the various embedded targets in my tester.  I'll wait \n>> for the RISC-V pre-commit CI tester to render a verdict before going \n>> forward.\n>>\n>>\n>> Jeff\n>>\n>>\n>> diff --git a/gcc/testsuite/gcc.target/riscv/pr124766.c b/gcc/testsuite/gcc.target/riscv/pr124766.c\n>> new file mode 100644\n>> index 000000000000..b16c31e8a9bd\n>> --- /dev/null\n>> +++ b/gcc/testsuite/gcc.target/riscv/pr124766.c\n>> @@ -0,0 +1,17 @@\n>> +/* { dg-do compile } */\n>> +/* { dg-options \"-march=rv64gcbv_zicond -mabi=lp64d\" { target rv64 } } */\n>> +/* { dg-options \"-march=rv32gcbv_zicond -mabi=ilp32\" { target rv32 } } */\n>> +/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n>> +\n>> +long\n>> +frob (unsigned short *y, long z)\n>> +{\n>> + long ret = (*y << 2) + z;\n>> + if (ret != z)\n>> + return 0;\n>> + return ret;\n>> +}\n>> +\n>> +/* { dg-final { scan-assembler-not \"sh2add\" } } */\n>> +/* { dg-final { scan-assembler-not \"sub\" } } */\n>> +\n>> diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc\n>> index 50fc51152cab..23de16800065 100644\n>> --- a/gcc/simplify-rtx.cc\n>> +++ b/gcc/simplify-rtx.cc\n>> @@ -6649,6 +6649,14 @@ simplify_context::simplify_relational_operation_1 (rtx_code code,\n>> return simplify_gen_relational (code, mode, cmp_mode, x, tem);\n>> }\n>> \n>> + /* (eq/ne (plus (x) (y)) y) simplifies to (eq/ne x 0). */\n>> + if ((code == EQ || code == NE)\n>> + && op0code == PLUS\n>> + && XEXP (op0, 1) == op1\n>\n> Looks like this would be better as rtx_equal_p, since it applies even\n> to y that aren't shared.\n\n...although I suppose that would also mean checking !side_effects_p (op1),\nsince we drop one instance.\n\n> Also...\n>\n>> + && (INTEGRAL_MODE_P (cmp_mode) || flag_unsafe_math_optimizations))\n>> + return simplify_gen_relational (code, mode, cmp_mode,\n>> +\t\t\t\t XEXP (op0, 0), const0_rtx);\n>\n> if we want to support the non-integral flag_unsafe_math_optimizations case,\n> we'd need to use CONST0_RTX (cmp_mode) instead of const0_rtx.\n>\n> Thanks,\n> Richard\n>\n>> +\n>> /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is\n>> the same as (zero_extract:SI FOO (const_int 1) BAR). */\n>> scalar_int_mode int_mode, int_cmp_mode;","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=googlemail.com header.i=@googlemail.com\n header.a=rsa-sha256 header.s=20251104 header.b=AP0JEH8g;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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charset=utf-8","Content-Transfer-Encoding":"quoted-printable","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3685461,"web_url":"http://patchwork.ozlabs.org/comment/3685461/","msgid":"<3a647579-7d49-4ebb-9411-572df1f2de8b@oss.qualcomm.com>","list_archive_url":null,"date":"2026-05-03T22:35:54","subject":"Re: [to-be-committed][RISC-V][PR rtl-optimization/124766] Simplify x\n + y == y into x == 0","submitter":{"id":92310,"url":"http://patchwork.ozlabs.org/api/people/92310/","name":"Jeffrey Law","email":"jeffrey.law@oss.qualcomm.com"},"content":"On 5/3/2026 1:03 PM, Richard Sandiford wrote:\n> Richard Sandiford writes:\n>> Jeffrey Law writes:\n>>> So this is derived from S_regmatch in spec2017, so fairly hot.\n>>>\n>>>\n>>>\n>>> long\n>>> frob (unsigned short *y, long z)\n>>> {\n>>>   long ret = (*y << 2) + z;\n>>>   if (ret != z)\n>>>     return 0;\n>>>   return ret;\n>>> }\n>>>\n>>> It generates this code on riscv:\n>>>\n>>>\n>>>         lhu     a5,0(a0)\n>>>         sh2add  a5,a5,a1\n>>>         sub     a1,a1,a5\n>>>         czero.nez       a0,a5,a1\n>>>         ret\n>>>\n>>> That's not bad, but the sh2add and sub are not actually needed. This may\n>>> look familiar to a case Daniel was recently discussing, the major\n>>> difference are the types of the function args which I got wrong the\n>>> first time I reduced this case.\n>>>\n>>> czero instructions check their condition for zero/nonzero status. So we\n>>> just need to know if a1 has a zero/nonzero value at the czero\n>>> instruction.  So working backwards\n>>>\n>>> a1 = a1 - a5                // sub instruction\n>>> a1 = a1 - ((a5 << 2) + a1)  // substitute from sh2add\n>>> a1 = a5 << 2                // a1 terms cancel out\n>>>\n>>> So we just need the nonzero state of a5 << 2.  Now since a5 was set by\n>>> the lhu instruction, the upper 48 bits are already known zero, so\n>>> critically we know the upper 2 bits are zero. Meaning that we can just\n>>> test a5 as set by the lhu instruction for zero/nonzero.  The net is we\n>>> can generate this code instead:\n>>>\n>>>         lhu     a0,0(a0)\n>>>         czero.nez       a0,a1,a0\n>>>         ret\n>>>\n>>>\n>>> It's a small, but visible instruction count savings and likely a small\n>>> performance improvement on most designs.\n>>>\n>>> So the trick to get there is a small simplify-rtx improvement. We just\n>>> need to simplify\n>>> (eq/ne (plus (x) (y)) (y)) ->  (eq/ne (x) (0))\n>>>\n>>> And all the right things just happen.  Bootstrapped and regression\n>>> tested on a variety of native platforms including x86, aarch64, riscv\n>>> and tested across the various embedded targets in my tester.  I'll wait\n>>> for the RISC-V pre-commit CI tester to render a verdict before going\n>>> forward.\n>>>\n>>>\n>>> Jeff\n>>>\n>>>\n>>> diff --git a/gcc/testsuite/gcc.target/riscv/pr124766.c b/gcc/testsuite/gcc.target/riscv/pr124766.c\n>>> new file mode 100644\n>>> index 000000000000..b16c31e8a9bd\n>>> --- /dev/null\n>>> +++ b/gcc/testsuite/gcc.target/riscv/pr124766.c\n>>> @@ -0,0 +1,17 @@\n>>> +/* { dg-do compile } */\n>>> +/* { dg-options \"-march=rv64gcbv_zicond -mabi=lp64d\" { target rv64 } } */\n>>> +/* { dg-options \"-march=rv32gcbv_zicond -mabi=ilp32\" { target rv32 } } */\n>>> +/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n>>> +\n>>> +long\n>>> +frob (unsigned short *y, long z)\n>>> +{\n>>> + long ret = (*y << 2) + z;\n>>> + if (ret != z)\n>>> + return 0;\n>>> + return ret;\n>>> +}\n>>> +\n>>> +/* { dg-final { scan-assembler-not \"sh2add\" } } */\n>>> +/* { dg-final { scan-assembler-not \"sub\" } } */\n>>> +\n>>> diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc\n>>> index 50fc51152cab..23de16800065 100644\n>>> --- a/gcc/simplify-rtx.cc\n>>> +++ b/gcc/simplify-rtx.cc\n>>> @@ -6649,6 +6649,14 @@ simplify_context::simplify_relational_operation_1 (rtx_code code,\n>>> return simplify_gen_relational (code, mode, cmp_mode, x, tem);\n>>> }\n>>> \n>>> + /* (eq/ne (plus (x) (y)) y) simplifies to (eq/ne x 0). */\n>>> + if ((code == EQ || code == NE)\n>>> + && op0code == PLUS\n>>> + && XEXP (op0, 1) == op1\n>> Looks like this would be better as rtx_equal_p, since it applies even\n>> to y that aren't shared.\n> ...although I suppose that would also mean checking !side_effects_p (op1),\n> since we drop one instance.\nAgreed on all three issues you've raised.  Thanks for catching them.  \nI'll do a sanity test with those.\n\nIt's always interesting.  Sometimes the time away from a patch, then \nlooking at it again months later makes some bugs/improvements painfully \nobvious.  Other times it's easy to forget that there were things to \nclean up...  Can't say if it's generally good or bad, but I've seen both \nhappen in my on efforts.\n\n\njeff","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=c1OPGXc3;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=heaFQGy+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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