[{"id":3685369,"web_url":"http://patchwork.ozlabs.org/comment/3685369/","msgid":"","list_archive_url":null,"date":"2026-05-03T11:58:58","subject":"Re: [x86 PATCH] Shorter load immediate constants with -Oz","submitter":{"id":808,"url":"http://patchwork.ozlabs.org/api/people/808/","name":"Uros Bizjak","email":"ubizjak@gmail.com"},"content":"On Sat, May 2, 2026 at 10:17 PM Roger Sayle wrote:\n>\n>\n> This patch adds two peephole2 patterns to i386.md to decrease the size\n> of some inteer loads. These replace \"movl $const, %eax\" (5 bytes)\n> with \"xorl %eax, %eax\" followed by either \"movb $const,%al\" or\n> \"movb $const,%ah\" (together 4 bytes), for suitable constants and\n> suitable genral registers, when the flags register is dead.\n>\n> Ideally modern Intel and AMD prcoessors can recognize these sequences\n> during instruction decode (avoiding any partial register stall in\n> the same way they avoid the false dependence for the xorl), and\n> internally generate a single uop, treating these bytes like an\n> alternate instruction encoding.\n>\n>\n> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap\n> and make -k check, both with and without --target_board=unix{-m32}\n> with no new failures. Ok for mainline?\n>\n>\n> 2026-05-02 Roger Sayle \n>\n> gcc/ChangeLog\n> PR target/32803\n> * config/i386/i386.md (peephole2): Don't transform xorl;movb into\n> movzb with -Oz.\n> (peephole2): Convert movl into xorl;movb (strict_low_part) with -Oz.\n> (peephole2): Likewise, convert movl into xorl;movb [abcd]h with -Oz.\n>\n> gcc/testsuite/ChangeLog\n> PR target/32803\n> * gcc.target/i386/pr32803-2.c: New test case.\n> * gcc.target/i386/pr32803-3.c: Likewise.\n\n+;; With -Oz, convert mov eax,200 (5 bytes) to xor eax,eax; mov al,200\n+;; (4 bytes) when the flags register is dead.\n+(define_peephole2\n+ [(set (match_operand:SWI48 0 \"general_reg_operand\")\n+ (match_operand:SWI48 1 \"const_int_operand\"))]\n+ \"optimize_insn_for_size_p () && optimize_size > 1\n+ && IN_RANGE (INTVAL (operands[1]), 128, 255)\n+ && peep2_regno_dead_p (0, FLAGS_REG)\"\n+ [(parallel [(set (match_dup 0) (const_int 0))\n+ (clobber (reg:CC FLAGS_REG))])\n+ (set (strict_low_part (match_dup 2)) (match_dup 3))]\n+{\n+ operands[2] = gen_lowpart (QImode, operands[0]);\n+ operands[3] = gen_int_mode (INTVAL (operands[1]), QImode);\n+})\n\nThis one will fail on 32-bit targets when trying to get QImode lowpart\nof %esi, %edi, %ebp (and %esp).\n\nUros.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=RJdnp93M;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3685432,"web_url":"http://patchwork.ozlabs.org/comment/3685432/","msgid":"","list_archive_url":null,"date":"2026-05-03T18:48:49","subject":"Re: [x86 PATCH] Shorter load immediate constants with -Oz","submitter":{"id":808,"url":"http://patchwork.ozlabs.org/api/people/808/","name":"Uros Bizjak","email":"ubizjak@gmail.com"},"content":"On Sat, May 2, 2026 at 10:17 PM Roger Sayle wrote:\n>\n>\n> This patch adds two peephole2 patterns to i386.md to decrease the size\n> of some inteer loads. These replace \"movl $const, %eax\" (5 bytes)\n> with \"xorl %eax, %eax\" followed by either \"movb $const,%al\" or\n> \"movb $const,%ah\" (together 4 bytes), for suitable constants and\n> suitable genral registers, when the flags register is dead.\n>\n> Ideally modern Intel and AMD prcoessors can recognize these sequences\n> during instruction decode (avoiding any partial register stall in\n> the same way they avoid the false dependence for the xorl), and\n> internally generate a single uop, treating these bytes like an\n> alternate instruction encoding.\n>\n>\n> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap\n> and make -k check, both with and without --target_board=unix{-m32}\n> with no new failures. Ok for mainline?\n>\n>\n> 2026-05-02 Roger Sayle \n>\n> gcc/ChangeLog\n> PR target/32803\n> * config/i386/i386.md (peephole2): Don't transform xorl;movb into\n> movzb with -Oz.\n> (peephole2): Convert movl into xorl;movb (strict_low_part) with -Oz.\n> (peephole2): Likewise, convert movl into xorl;movb [abcd]h with -Oz.\n>\n> gcc/testsuite/ChangeLog\n> PR target/32803\n> * gcc.target/i386/pr32803-2.c: New test case.\n> * gcc.target/i386/pr32803-3.c: Likewise.\n\n+;; With -Oz, convert mov eax,200 (5 bytes) to xor eax,eax; mov al,200\n+;; (4 bytes) when the flags register is dead.\n+(define_peephole2\n+ [(set (match_operand:SWI48 0 \"general_reg_operand\")\n\nPlease use any_QIreg_operand predicate here to avoid generating\ninvalid QI registers on 32-bit targets.\n\n+ (match_operand:SWI48 1 \"const_int_operand\"))]\n+ \"optimize_insn_for_size_p () && optimize_size > 1\n+ && IN_RANGE (INTVAL (operands[1]), 128, 255)\n+ && peep2_regno_dead_p (0, FLAGS_REG)\"\n+ [(parallel [(set (match_dup 0) (const_int 0))\n+ (clobber (reg:CC FLAGS_REG))])\n+ (set (strict_low_part (match_dup 2)) (match_dup 3))]\n+{\n+ operands[2] = gen_lowpart (QImode, operands[0]);\n+ operands[3] = gen_int_mode (INTVAL (operands[1]), QImode);\n+})\n+\n+;; With -Oz, convert mov eax,512 (5 bytes) to xor eax,eax; mov ah,2\n+;; (4 bytes) when the flags register is dead.\n+(define_peephole2\n+ [(set (match_operand:SWI48 0 \"general_reg_operand\")\n\nPlease use QIreg_operand predicate here instead of QI_REGNO_P\npredicate in insn constraint.\n\n+ (match_operand:SWI48 1 \"const_int_operand\"))]\n+ \"optimize_insn_for_size_p () && optimize_size > 1\n+ && (INTVAL (operands[1]) & ~0xff00) == 0\n+ && QI_REGNO_P (REGNO (operands[0]))\n+ && peep2_regno_dead_p (0, FLAGS_REG)\"\n+ [(parallel [(set (match_dup 0) (const_int 0))\n+ (clobber (reg:CC FLAGS_REG))])\n+ (set (zero_extract:SWI48 (match_dup 0) (const_int 8) (const_int 8))\n+ (match_dup 2))]\n+ \"operands[2] = gen_int_mode (INTVAL (operands[1]) >> 8, QImode);\")\n\nUros.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=jw4vMkIs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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