[{"id":3685211,"web_url":"http://patchwork.ozlabs.org/comment/3685211/","msgid":"<2ce5897d-5bbb-486a-b0f0-0e30e54b451a@lunn.ch>","list_archive_url":null,"date":"2026-05-01T19:04:58","subject":"Re: [PATCH net-next 10/12] net: stmmac: tc956x: add TC956x/QPS615\n support","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> +static struct tc956x_mac_speed mac_speed[] = {\n> +\t{ PHY_INTERFACE_MODE_2500BASEX,\tSPEED_2500,  SP_SEL_SGMII_2500M, },\n> +\t{ PHY_INTERFACE_MODE_SGMII,\tSPEED_2500,  SP_SEL_SGMII_2500M, },\n> +\t{ PHY_INTERFACE_MODE_SGMII,\tSPEED_1000,  SP_SEL_SGMII_1000M, },\n\nThat looks odd. Some vendors implemented 2500BaseX using SGMII\noverclocked. But that is not strictly 2500BaseX. Having the 2500BASEX\nentry suggests you have real 2500BASEX, so why have an SGMII entry\nwith SPEED_2500?\n\n> +/* We have one IRQ chip instance with 25 IRQs in its domain */\n\nOne per MAC, or one overall?\n\n> +static struct irq_domain *\n> +tc956x_msigen_irq_domain_instantiate(struct tc956x_data *td)\n> +{\n> +\tstruct irq_domain_chip_generic_info dgc_info;\n> +\tstruct irq_domain_info info;\n> +\n> +\tdgc_info.name = \"tc956x-msigen\";\n\nIf it is one per MAC, maybe this name should indicate which instance\nof the MAC this is.\n\n> +static int tc956x_mac_setup(void *apriv, struct mac_device_info *mac)\n> +{\n> +\tstruct stmmac_priv *priv = apriv;\n> +\tstruct stmmac_desc_ops *desc;\n> +\tstruct stmmac_dma_ops *dma;\n> +\tstruct tc956x_data *td;\n> +\n> +\ttd = priv->plat->bsp_priv;\n> +\n> +\t/* dwxgmac301_dma_ops needs extending to provide DMA address translation */\n> +\tdma = &td->dma;\n> +\t*dma = dwxgmac301_dma_ops;\n> +\tdma->init_rx_chan = tc956x_dma_init_rx_chan;\n> +\tdma->init_tx_chan = tc956x_dma_init_tx_chan;\n> +\tmac->dma = dma;\n\nI could be reading this wrong....\n\ndma points to the global dwxgmac301_dma_ops, which you added a few\npatches back.\n\nYou then modify it, changing two values in it.\n\nDoesn't that break any other dwxgmac301 in the system? Shouldn't you\nbe making a copy of the global structure, and then making\nmodifications to your copy? mac->dma then points to your copy?\n\n> +\t/* dwxgmac210_desc_ops also needs extending for the same reason */\n> +\tdesc = &td->desc;\n> +\t*desc = dwxgmac210_desc_ops;\n> +\tdesc->set_addr = tc956x_desc_set_addr;\n> +\tdesc->set_sec_addr = tc956x_desc_set_sec_addr;\n> +\tmac->desc = desc;\n\nAnd the same problem here?\n\n> +/* Called by tc956x_dwmac_probe(); return errors with dev_err_probe() */\n> +static int tc956x_dwmac_parse_dt(struct tc956x_data *td)\n> +{\n> +\tstruct device_node *mdio_node;\n> +\tstruct device *dev = td->dev;\n> +\tstruct device_node *np;\n> +\n> +\tnp = dev_of_node(dev);\n> +\tif (!np)\n> +\t\treturn dev_err_probe(dev, -EINVAL, \"no devicetree node\\n\");\n> +\n> +\t/* Find the MDIO bus */\n> +\tfor_each_child_of_node(np, mdio_node) {\n> +\t\tif (of_device_is_compatible(mdio_node,\n> +\t\t\t\t\t    \"snps,dwmac-mdio\"))\n> +\t\t\tbreak;\n> +\t}\n\nIt looks like if you put the ethernet properties into an ethernet node\nin DT, this might go away? Or at least allow you to use\nstmmac_of_get_mdio(). \n\n\tAndrew","headers":{"Return-Path":"\n <linux-gpio+bounces-35973-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256\n header.s=20171124 header.b=2aopWn4Z;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35973-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch\n header.b=\"2aopWn4Z\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=156.67.10.101","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=lunn.ch","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=lunn.ch"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6gW11Rk5z1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 02 May 2026 05:06:21 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 7F798301703C\n\tfor <incoming@patchwork.ozlabs.org>; Fri,  1 May 2026 19:05:37 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 7210439B482;\n\tFri,  1 May 2026 19:05:36 +0000 (UTC)","from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id C87CE209F43;\n\tFri,  1 May 2026 19:05:34 +0000 (UTC)","from andrew by vps0.lunn.ch with local (Exim 4.94.2)\n\t(envelope-from <andrew@lunn.ch>)\n\tid 1wItAY-000rhF-A4; Fri, 01 May 2026 21:04:58 +0200"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777662336; cv=none;\n b=p331A2Td8R33SZ+P7EwDZHvP246rK40a/OkW4fwMDKmPKZdSQ1IryjBGPhiH2+jOV2yqvG1uAAM87C+KFo+uY965fvLzAQ2N7emZ4jWwz4DtgimvLRbSDQYl/NANg+Vo4S7OPAbCsXnyu2Nmn87Dvq5A+VxXVEajTsIXJN22HPk=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777662336; c=relaxed/simple;\n\tbh=ufnSYvn8Uzt3nTQsV1VJKLbQYH3r3L0bOIJ7Sm6Df/I=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=dwxbdJc9OWwBsb+juNLpfdL1sqzxyCtjkmQJWOXR8/lTu57gohHvy0SGCjf+STRzEsixhebddSSh7c2MSMADRbeDVhAC2KwtUmO8Cw1pkGoSUDU77pI37s0tgovhFj9nkdZnQvFE29xfizLZLjgTzOK05Ljm/f6HdDOL+W0xYNA=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=lunn.ch;\n spf=pass smtp.mailfrom=lunn.ch;\n dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch\n header.b=2aopWn4Z; arc=none smtp.client-ip=156.67.10.101","DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch;\n\ts=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version:\n\tReferences:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject:\n\tDate:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:\n\tContent-ID:Content-Description:Content-Disposition:In-Reply-To:References;\n\tbh=zr1miL8fEoh0znlRNbkoD7ZZWFwQTcpiCWJezhzfkWE=; b=2aopWn4ZWWUJPQxJ+ht/UIkJ+v\n\tvkgJl4IX6j5VZk1n6LbGHadysUccJ0QjcoSvhvw+ZCdXCpfCcEu1ihL2mKiw6RYni+9knLTq2t0vX\n\t+q4DH2uZbxMRfss3zSE9cotXt7E9cBZC5jZ+/6EerFlTpjUtJZiVrk8Ug/y2Bv4FjvC8=;","Date":"Fri, 1 May 2026 21:04:58 +0200","From":"Andrew Lunn <andrew@lunn.ch>","To":"Alex Elder <elder@riscstar.com>","Cc":"andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,\n\tkuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com,\n\trmk+kernel@armlinux.org.uk, andersson@kernel.org,\n\tkonradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org,\n\tconor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org,\n\tarnd@arndb.de, gregkh@linuxfoundation.org,\n\tDaniel Thompson <daniel@riscstar.com>, mohd.anwar@oss.qualcomm.com,\n\ta0987203069@gmail.com, alexandre.torgue@foss.st.com, ast@kernel.org,\n\tboon.khai.ng@altera.com, chenchuangyu@xiaomi.com,\n\tchenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org,\n\thkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com,\n\tjulianbraha@gmail.com, livelycarpet87@gmail.com,\n\tmatthew.gerlach@altera.com, mcoquelin.stm32@gmail.com, me@ziyao.cc,\n\tprabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com,\n\trohan.g.thomas@altera.com, sdf@fomichev.me,\n\tsiyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com,\n\twens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org,\n\tlinux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tlinux-stm32@st-md-mailman.stormreply.com,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH net-next 10/12] net: stmmac: tc956x: add TC956x/QPS615\n support","Message-ID":"<2ce5897d-5bbb-486a-b0f0-0e30e54b451a@lunn.ch>","References":"<20260501155421.3329862-1-elder@riscstar.com>\n <20260501155421.3329862-11-elder@riscstar.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"<linux-gpio.vger.kernel.org>","List-Subscribe":"<mailto:linux-gpio+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:linux-gpio+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260501155421.3329862-11-elder@riscstar.com>"}}]