[{"id":3685182,"web_url":"http://patchwork.ozlabs.org/comment/3685182/","msgid":"<91332fc1-11ed-444e-a211-699420cf0108@lunn.ch>","list_archive_url":null,"date":"2026-05-01T17:06:15","subject":"Re: [PATCH net-next 03/12] net: pcs: pcs-xpcs: Preserve BMCR_ANENBLE\n during link up","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"On Fri, May 01, 2026 at 10:54:11AM -0500, Alex Elder wrote:\n> From: Daniel Thompson \n> \n> Currently the XCPS found on Toshiba TC9564 (a.k.a. Qualcomm QPS615)\n> is unable to operate at 1000base-X and slower with a PHY connected\n> using SGMII/2500base-X (in our case a Qualcomm QCA8081). The link\n> negotiates speed correctly but the MAC can't get any packets out.\n\nWe need to break this down into its components.\n\nI assume you are saying the PHY negotiates the media speed with the\nlink partner. That is PHY talking to PHY.\n\nBut we also have the PCS talking to the PHY. There can be inband\nsignalling here, for SGMII and 2500BaseX. But not for over clocked\nSGMII, which is how some vendors implement 2500BaseX. SGMII signalling\ndoes not work when overclocked to 2.5G.\n\n> This attracted attention to the ANENABLE bit and we observed that the\n> bit is currently set during config and cleared during link up.\n\nHere we are talking about the PCS ANEBNABLE, not the PHY ANEBNABLE. So\nthis is negotiation between the PCS and the PHY.\n\n> Preserving the bit during link up allows the system to work as expected.\n\n> \tint ret;\n> \n> \tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)\n> \t\treturn;\n\nThink about this.\n\n> \tret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,\n> -\t\t\t mii_bmcr_encode_fixed(speed, duplex));\n> +\t\t\t mii_bmcr_encode_fixed(speed, duplex) | an_enable);\n\nAnd mii_bmcr_encode_fixed().\n\n Andrew","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256\n header.s=20171124 header.b=znFlC6Z1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35966-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch\n header.b=\"znFlC6Z1\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=156.67.10.101","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=lunn.ch","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=lunn.ch"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6cv951pHz1xvV\n\tfor ; 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b=znFlC6Z1LbaPEB8hdbXzJvnLmX\n\tZBb5bVF2HsqCqy7NL8xzUAScLF3GtUTr2nfELsGPhw5RG6eMWlshgtivDVmVnuBJG1PPwK2X/OEFw\n\t7Pwq/+yrfBQMddetIGMjgb6xDlSbYL5+c3pO1lHwmCZw38A89SyejKB1b5Jl0htXaRDk=;","Date":"Fri, 1 May 2026 19:06:15 +0200","From":"Andrew Lunn ","To":"Alex Elder ","Cc":"andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,\n\tkuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com,\n\trmk+kernel@armlinux.org.uk, andersson@kernel.org,\n\tkonradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org,\n\tconor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org,\n\tarnd@arndb.de, gregkh@linuxfoundation.org,\n\tDaniel Thompson , mohd.anwar@oss.qualcomm.com,\n\ta0987203069@gmail.com, alexandre.torgue@foss.st.com, ast@kernel.org,\n\tboon.khai.ng@altera.com, chenchuangyu@xiaomi.com,\n\tchenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org,\n\thkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com,\n\tjulianbraha@gmail.com, livelycarpet87@gmail.com,\n\tmatthew.gerlach@altera.com, mcoquelin.stm32@gmail.com, me@ziyao.cc,\n\tprabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com,\n\trohan.g.thomas@altera.com, sdf@fomichev.me,\n\tsiyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com,\n\twens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org,\n\tlinux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tlinux-stm32@st-md-mailman.stormreply.com,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH net-next 03/12] net: pcs: pcs-xpcs: Preserve BMCR_ANENBLE\n during link up","Message-ID":"<91332fc1-11ed-444e-a211-699420cf0108@lunn.ch>","References":"<20260501155421.3329862-1-elder@riscstar.com>\n <20260501155421.3329862-4-elder@riscstar.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; 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