[{"id":3685251,"web_url":"http://patchwork.ozlabs.org/comment/3685251/","msgid":"<4ce9f13a-b17f-4149-ade8-57519f4a4752@ti.com>","list_archive_url":null,"date":"2026-05-02T05:18:14","subject":"Re: [PATCH 1/2] PCI: cadence: Ensure that\n cdns_pcie_host_wait_for_link() waits 100 ms after link up","submitter":{"id":84157,"url":"http://patchwork.ozlabs.org/api/people/84157/","name":"Siddharth Vadapalli","email":"s-vadapalli@ti.com"},"content":"On 01/05/26 21:05, Hans Zhang wrote:\n> As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds\n> greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link\n> training completes before sending a Configuration Request.\n> \n> Add a new 'max_link_speed' field in struct cdns_pcie to record the\n> maximum supported (or currently configured) link speed of the controller.\n> \n> In cdns_pcie_host_wait_for_link(), after the link is reported as up,\n> insert a 100 ms delay if max_link_speed > 2 (i.e., > 5 GT/s). This\n> implements the required delay at the common Cadence host layer.\n> \n> Currently max_link_speed is zero-initialized, so the delay is not yet\n> active. Glue drivers must set max_link_speed appropriately to enable\n> the delay. This matches the approach taken for the Synopsys DWC\n> controller in commit 80dc18a0cba8d (\"PCI: dwc: Ensure that\n> dw_pcie_wait_for_link() waits 100 ms after link up\").\n> \n> Signed-off-by: Hans Zhang <18255117159@163.com>\n> ---\n> .../pci/controller/cadence/pcie-cadence-host-common.c | 9 +++++++++\n> drivers/pci/controller/cadence/pcie-cadence.h | 2 ++\n> 2 files changed, 11 insertions(+)\n> \n> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n> index 2b0211870f02..d4ae762f423f 100644\n> --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n> +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n> @@ -14,6 +14,7 @@\n> \n> #include \"pcie-cadence.h\"\n> #include \"pcie-cadence-host-common.h\"\n> +#include \"../../pci.h\"\n> \n> #define LINK_RETRAIN_TIMEOUT HZ\n> \n> @@ -55,6 +56,14 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,\n> \t/* Check if the link is up or not */\n> \tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n> \t\tif (pcie_link_up(pcie)) {\n> +\t\t\t/*\n> +\t\t\t * As per PCIe r6.0, sec 6.6.1, a Downstream Port that\n> +\t\t\t * supports Link speeds greater than 5.0 GT/s, software\n> +\t\t\t * must wait a minimum of 100 ms after Link training\n> +\t\t\t * completes before sending a Configuration Request.\n> +\t\t\t */\n> +\t\t\tif (pcie->max_link_speed > 2)\n> +\t\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n\nI think the above could be moved to cdns_pcie_host_start_link() as follows:\n\ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c \nb/drivers/pci/controller/cadence/pcie-cadence-host-common.c\nindex 2b0211870f02..0f885dcbdb12 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n@@ -115,6 +115,15 @@ int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc,\n \tif (!ret && rc->quirk_retrain_flag)\n \t\tret = cdns_pcie_retrain(pcie, pcie_link_up);\n\n+\t/*\n+\t * As per PCIe r6.0, sec 6.6.1, a Downstream Port that\n+\t * supports Link speeds greater than 5.0 GT/s, software\n+\t * must wait a minimum of 100 ms after Link training\n+\t * completes before sending a Configuration Request.\n+\t */\n+\tif (!ret && pcie->max_link_speed > 2)\n+\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n+\n \treturn ret;\n }\n EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link);\n\nThis will avoid an additional and unnecessary delay when \n'cdns_pcie_retrain()' retrains the link.\n\nInstead of checking for the link being up using \"pcie_link_up(pcie)\", \nchecking for 'ret' being zero should also work (ret being zero indicates \nthat the link is up).\n\nSince configuration space accesses will not be performed until \ncdns_pcie_host_start_link() completes executing, it should be safe to \nswitch to the above implementation.\n\n\n> \t\t\tdev_info(dev, \"Link up\\n\");\n> \t\t\treturn 0;\n> \t\t}\n\n[TRIMMED]\n\nRegards,\nSiddharth.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=selector1 header.b=X8y78tbE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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helo=lewvzet201.ext.ti.com; pr=C","Message-ID":"<4ce9f13a-b17f-4149-ade8-57519f4a4752@ti.com>","Date":"Sat, 2 May 2026 10:48:14 +0530","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","CC":", , ,\n\t, , ,\n\t, ,\n\t, ,\n\t","Subject":"Re: [PATCH 1/2] PCI: cadence: Ensure that\n cdns_pcie_host_wait_for_link() waits 100 ms after link up","To":"Hans Zhang <18255117159@163.com>","References":"<20260501153553.66382-1-18255117159@163.com>\n <20260501153553.66382-2-18255117159@163.com>","Content-Language":"en-US","From":"Siddharth Vadapalli ","In-Reply-To":"<20260501153553.66382-2-18255117159@163.com>","Content-Type":"text/plain; charset=\"UTF-8\"; format=flowed","Content-Transfer-Encoding":"7bit","X-C2ProcessedOrg":"333ef613-75bf-4e12-a4b1-8e3623f5dcea","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"CH3PEPF00000015:EE_|CY8PR10MB7220:EE_","X-MS-Office365-Filtering-Correlation-Id":"40ec5ca9-7d88-40e6-1720-08dea809e552","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|1800799024|376014|7416014|36860700016|82310400026|56012099003|22082099003|18002099003;","X-Microsoft-Antispam-Message-Info":"\n\t1DMlFSZl82TRajtb08J8jsXbOxCF6f+pbHI96YpvPF70D7nEtj4nGwqYOARMtJEFrcdUFRRzumi57aOEWaqHAAdH6W/Q4voLJs+pXugA1RkB7xZhj1pLDv4ERLYfXrUxNiZz23BtUxZplnyn7/ocUqBMaJjbG/pa3OOHGrcXTrPhax0gHUZJWLjCVzp+Og7LLlr8wrvxhlqsyMeCV5ott3Wq3kJTmbWZUgIKgkhtlaen0OD/GmarYuucY/VEN2vnvj60CGdaOapMYYXEFyc/ku806mrot2izXsed+zQO4VpYiLm/Q6yPcvDzRmQxd4JGzobsgnE2EddYHMGnO2az6lvysCOyprPmcaJimA7GEGxbqejj2SjUfP+kGlQqeJgwy5ibFF/Tju45I0m69ki9Xn12auJREYvVHBQI0yLOyIS7csno/XaDGjmLVVHXJDZI2MW6srgs6rkS5lXji9BChEZ8qq4pw2MmU3QMaMcBfJxPZoRIH16Z8V+KVR1QmP4iNRBXDcaxZNp1Q79sETaJeV/ZXxSyXPyPgRMSb9HRTUL0LVeq546kk55yqKfhX+w5kSy3XY41iyB4mjCU5CSpTzwuC6b17Ssw4geKd38mlEmpvD1yU7OEDuc1XnfgvrU2pzSLe6UdZrIKCA74bKsGHLsobCVsXget5tNfb6ES09hGIebdLeNE4jSOcQzUyF2XzGMAxBF/kuZMbFFQR01Gz00aPUNKC7QoZxaUfJEuzbA=","X-Forefront-Antispam-Report":"\n\tCIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700016)(82310400026)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\teFltndShEC7JM4E8AezFGMXXL68G+BjbPl38QbWROyryXTGmu6eDDQ9QkXvKy0XkFCHzwtxOZDjFK+EKT2K2AkWRg4JALwmVFJuLpijU2+ftHk+q4erMKwIOjQiJbDq8YUQUVS9z53hSGfvu+fDDW3QyOs4ZQHDMwmHVnaltZYScQYMAru+7DVY7Xyd+LIEk8P4knl94Pg788R9PZX0wM357qMaYElRda8+fq8p5b/PFI2bFORDA/t47GzPA0vmcxGKz5P+irkSZ5JNzFy8KTUCAhaymemCdZlyq484wDvHTZ5Tn0uv/xJl1jBm9Fu4fA0We2k0uj7R6FbJsgGSUeH3yc34zVIVMwQ0uTfBNFrt8IuW10tyfe4i/ptKAyDBNLP4Vv5qXZu7FyJX5Y6y/z+q9V9EQW9Aac4o9cELvcOWHfJLqzItkkDR5DKQkfjJ2","X-OriginatorOrg":"ti.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"02 May 2026 05:15:58.7816\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 40ec5ca9-7d88-40e6-1720-08dea809e552","X-MS-Exchange-CrossTenant-Id":"e5b49634-450b-4709-8abb-1e2b19b982b7","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tCH3PEPF00000015.namprd21.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY8PR10MB7220"}}]