[{"id":3684624,"web_url":"http://patchwork.ozlabs.org/comment/3684624/","msgid":"","list_archive_url":null,"date":"2026-04-30T11:33:48","subject":"Re: [Intel-wired-lan] [PATCH v7 net-next 8/8] ice: implement E825\n TX ref clock control and TXC hardware sync status","submitter":{"id":75597,"url":"http://patchwork.ozlabs.org/api/people/75597/","name":"Aleksandr Loktionov","email":"aleksandr.loktionov@intel.com"},"content":"> -----Original Message-----\n> From: Intel-wired-lan On Behalf\n> Of Grzegorz Nitka\n> Sent: Thursday, April 30, 2026 11:43 AM\n> To: netdev@vger.kernel.org\n> Cc: Vecera, Ivan ; vadim.fedorenko@linux.dev;\n> kuba@kernel.org; jiri@resnulli.us; edumazet@google.com; Kitszel,\n> Przemyslaw ; richardcochran@gmail.com;\n> donald.hunter@gmail.com; linux-kernel@vger.kernel.org; Kubalewski,\n> Arkadiusz ; andrew+netdev@lunn.ch;\n> intel-wired-lan@lists.osuosl.org; horms@kernel.org;\n> Prathosh.Satish@microchip.com; Nguyen, Anthony L\n> ; pabeni@redhat.com; davem@davemloft.net\n> Subject: [Intel-wired-lan] [PATCH v7 net-next 8/8] ice: implement E825\n> TX ref clock control and TXC hardware sync status\n> \n> Build on the previously introduced TXC DPLL framework and implement\n> full TX reference clock control and hardware-backed synchronization\n> status reporting for E825 devices.\n> \n> E825 firmware may accept or override TX reference clock requests based\n> on device-wide routing constraints and link conditions. For this\n> reason, TX reference selection and synchronization status must be\n> observed from hardware rather than inferred from user intent.\n> \n> This change implements TX reference switching using a deferred worker,\n> triggered by DPLL TXCLK pin operations. Pin set callbacks express\n> selection intent and schedule the operation asynchronously; firmware\n> commands and autonegotiation restarts are executed outside of DPLL\n> context.\n> \n> After link-up, the effective TX reference clock is read back from\n> hardware and software state is reconciled accordingly. TXCLK pin state\n> reflects only the selected reference clock topology:\n> - External references (SYNCE, EREF0) are represented as TXCLK pins\n> - The internal ENET/TXCO clock has no pin representation; when\n> selected,\n> all TXCLK pins are reported DISCONNECTED\n> \n> Actual hardware synchronization result is reported exclusively via the\n> TXC DPLL lock status:\n> - LOCKED when an external TX reference is in use\n> - UNLOCKED when falling back to ENET/TXCO\n> \n> This separation allows userspace to distinguish between TX reference\n> selection and successful synchronization, matching the DPLL subsystem\n> model where pin state describes topology and device lock status\n> describes signal quality.\n> \n> With this change, TX reference clocks on E825 devices can be reliably\n> selected, verified against hardware state, and monitored for effective\n> synchronization via standard DPLL interfaces.\n> \n> Reviewed-by: Arkadiusz Kubalewski \n> Signed-off-by: Grzegorz Nitka \n> ---\n> drivers/net/ethernet/intel/ice/Makefile | 2 +-\n> drivers/net/ethernet/intel/ice/ice.h | 12 +\n> drivers/net/ethernet/intel/ice/ice_dpll.c | 110 ++++++++-\n> drivers/net/ethernet/intel/ice/ice_dpll.h | 4 +\n> drivers/net/ethernet/intel/ice/ice_ptp.c | 26 +-\n> drivers/net/ethernet/intel/ice/ice_ptp.h | 7 +\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 37 +++\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 27 +++\n> drivers/net/ethernet/intel/ice/ice_txclk.c | 255 ++++++++++++++++++++\n> drivers/net/ethernet/intel/ice/ice_txclk.h | 38 +++\n> 10 files changed, 499 insertions(+), 19 deletions(-) create mode\n> 100644 drivers/net/ethernet/intel/ice/ice_txclk.c\n> create mode 100644 drivers/net/ethernet/intel/ice/ice_txclk.h\n> \n> diff --git a/drivers/net/ethernet/intel/ice/Makefile\n> b/drivers/net/ethernet/intel/ice/Makefile\n> index 38db476ab2ec..95fd0c49800f 100644\n> --- a/drivers/net/ethernet/intel/ice/Makefile\n> +++ b/drivers/net/ethernet/intel/ice/Makefile\n> @@ -54,7 +54,7 @@ ice-$(CONFIG_PCI_IOV) +=\t\\\n> \tice_vf_mbx.o\t\t\\\n> \tice_vf_vsi_vlan_ops.o\t\\\n> \tice_vf_lib.o\n> -ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o ice_dpll.o\n> ice_tspll.o ice_cpi.o\n> +ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o ice_dpll.o\n> +ice_tspll.o ice_cpi.o ice_txclk.o\n> ice-$(CONFIG_DCB) += ice_dcb.o ice_dcb_nl.o ice_dcb_lib.o\n> ice-$(CONFIG_RFS_ACCEL) += ice_arfs.o\n> ice-$(CONFIG_XDP_SOCKETS) += ice_xsk.o\n> diff --git a/drivers/net/ethernet/intel/ice/ice.h\n> b/drivers/net/ethernet/intel/ice/ice.h\n> index 725b130dd3a2..f72bb1aa4067 100644\n> --- a/drivers/net/ethernet/intel/ice/ice.h\n> +++ b/drivers/net/ethernet/intel/ice/ice.h\n> @@ -1155,4 +1155,16 @@ static inline struct ice_hw\n> *ice_get_primary_hw(struct ice_pf *pf)\n> \telse\n> \t\treturn &pf->adapter->ctrl_pf->hw;\n> }\n\n...\n\n> * * negative - failure\n> */\n> static int\n> @@ -2547,11 +2586,29 @@ ice_dpll_txclk_state_on_dpll_set(const struct\n> dpll_pin *pin, void *pin_priv,\n> \t\t\t\t void *dpll_priv, enum dpll_pin_state\n> state,\n> \t\t\t\t struct netlink_ext_ack *extack)\n> {\n> -\t/*\n> -\t * TODO: set HW accordingly to selected TX reference clock.\n> -\t * To be added in the follow up patches.\n> -\t */\n> -\treturn -EOPNOTSUPP;\n> +\tstruct ice_dpll_pin *p = pin_priv;\n> +\tstruct ice_pf *pf = p->pf;\n> +\tenum ice_e825c_ref_clk new_clk;\n> +\n> +\tif (ice_dpll_is_reset(pf, extack))\n> +\t\treturn -EBUSY;\n> +\n> +\tmutex_lock(&pf->dplls.lock);\n> +\tnew_clk = (state == DPLL_PIN_STATE_DISCONNECTED) ?\n> ICE_REF_CLK_ENET :\n> +\t\t\tp->tx_ref_src;\n> +\tif (new_clk == pf->ptp.port.tx_clk_req) {\n> +\t\tNL_SET_ERR_MSG_FMT(extack,\n> +\t\t\t\t \"pin:%u state:%u on parent device\n> already set\",\n> +\t\t\t\t p->idx, state);\n> +\t\tgoto unlock;\nextack message attached, but ...\n\n> +\t}\n> +\n> +\tpf->ptp.port.tx_clk_req = new_clk;\n> +\tpf->dplls.txclk_switch_requested = true;\n> +\tqueue_work(pf->dplls.wq, &pf->dplls.txclk_work);\n> +unlock:\n> +\tmutex_unlock(&pf->dplls.lock);\n> +\treturn 0;\n... function returns success.\nIMHO either drop the message or return -EALREADY/-EBUSY.\nOr I missed something?\n\n> }\n> \n> /**\n> @@ -2563,10 +2620,21 @@ ice_dpll_txclk_state_on_dpll_set(const struct\n> dpll_pin *pin, void *pin_priv,\n> * @state: on success holds pin state on parent pin\n> * @extack: error reporting\n> *\n\n...\n\n> --\n> 2.39.3","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=PGI+eI+Z;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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vadim.fedorenko@linux.dev;\n> kuba@kernel.org; jiri@resnulli.us; edumazet@google.com; Kitszel,\n> Przemyslaw ; richardcochran@gmail.com;\n> donald.hunter@gmail.com; linux-kernel@vger.kernel.org; Kubalewski,\n> Arkadiusz ; andrew+netdev@lunn.ch;\n> intel-wired-lan@lists.osuosl.org; horms@kernel.org;\n> Prathosh.Satish@microchip.com; Nguyen, Anthony L\n> ; pabeni@redhat.com; davem@davemloft.net\n> Subject: [Intel-wired-lan] [PATCH v7 net-next 8/8] ice: implement E825\n> TX ref clock control and TXC hardware sync status\n> \n> Build on the previously introduced TXC DPLL framework and implement\n> full TX reference clock control and hardware-backed synchronization\n> status reporting for E825 devices.\n> \n> E825 firmware may accept or override TX reference clock requests based\n> on device-wide routing constraints and link conditions. For this\n> reason, TX reference selection and synchronization status must be\n> observed from hardware rather than inferred from user intent.\n> \n> This change implements TX reference switching using a deferred worker,\n> triggered by DPLL TXCLK pin operations. Pin set callbacks express\n> selection intent and schedule the operation asynchronously; firmware\n> commands and autonegotiation restarts are executed outside of DPLL\n> context.\n> \n> After link-up, the effective TX reference clock is read back from\n> hardware and software state is reconciled accordingly. TXCLK pin state\n> reflects only the selected reference clock topology:\n> - External references (SYNCE, EREF0) are represented as TXCLK pins\n> - The internal ENET/TXCO clock has no pin representation; when\n> selected,\n> all TXCLK pins are reported DISCONNECTED\n> \n> Actual hardware synchronization result is reported exclusively via the\n> TXC DPLL lock status:\n> - LOCKED when an external TX reference is in use\n> - UNLOCKED when falling back to ENET/TXCO\n> \n> This separation allows userspace to distinguish between TX reference\n> selection and successful synchronization, matching the DPLL subsystem\n> model where pin state describes topology and device lock status\n> describes signal quality.\n> \n> With this change, TX reference clocks on E825 devices can be reliably\n> selected, verified against hardware state, and monitored for effective\n> synchronization via standard DPLL interfaces.\n> \n> Reviewed-by: Arkadiusz Kubalewski \n> Signed-off-by: Grzegorz Nitka \n> ---\n> drivers/net/ethernet/intel/ice/Makefile | 2 +-\n> drivers/net/ethernet/intel/ice/ice.h | 12 +\n> drivers/net/ethernet/intel/ice/ice_dpll.c | 110 ++++++++-\n> drivers/net/ethernet/intel/ice/ice_dpll.h | 4 +\n> drivers/net/ethernet/intel/ice/ice_ptp.c | 26 +-\n> drivers/net/ethernet/intel/ice/ice_ptp.h | 7 +\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 37 +++\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 27 +++\n> drivers/net/ethernet/intel/ice/ice_txclk.c | 255 ++++++++++++++++++++\n> drivers/net/ethernet/intel/ice/ice_txclk.h | 38 +++\n> 10 files changed, 499 insertions(+), 19 deletions(-) create mode\n> 100644 drivers/net/ethernet/intel/ice/ice_txclk.c\n> create mode 100644 drivers/net/ethernet/intel/ice/ice_txclk.h\n> \n> diff --git a/drivers/net/ethernet/intel/ice/Makefile\n> b/drivers/net/ethernet/intel/ice/Makefile\n> index 38db476ab2ec..95fd0c49800f 100644\n> --- a/drivers/net/ethernet/intel/ice/Makefile\n> +++ b/drivers/net/ethernet/intel/ice/Makefile\n> @@ -54,7 +54,7 @@ ice-$(CONFIG_PCI_IOV) +=\t\\\n> \tice_vf_mbx.o\t\t\\\n> \tice_vf_vsi_vlan_ops.o\t\\\n> \tice_vf_lib.o\n\n...\n\n> \n> +/**\n> + * ice_dpll_txclk_work - apply a pending TX reference clock change\n> + * @work: work_struct embedded in struct ice_dplls\n> + *\n> + * This worker executes an outstanding TX reference clock switch\n> +request\n> + * that was previously queued via the DPLL TXCLK pin set callback.\n> + *\n> + * The worker performs only the operational part of the switch,\n> issuing\n> + * the necessary firmware commands to request a new TX reference\n> clock\n> + * selection (e.g. triggering an AN restart). It does not verify\n> +whether\n> + * the requested clock was ultimately accepted by the hardware.\n> + *\n> + * Hardware verification, software state reconciliation, pin state\n> + * notification, and TXC DPLL lock-status updates are performed\n> later,\n> + * after link-up, by ice_txclk_update_and_notify().\n> + *\n> + * Context:\n> + * - Runs in process context on pf->dplls.wq and may sleep.\n> + * - Serializes access to shared TXCLK state using pf->dplls.lock.\n> + */\n> +static void ice_dpll_txclk_work(struct work_struct *work) {\n> +\tstruct ice_dplls *dplls =\n> +\t\tcontainer_of(work, struct ice_dplls, txclk_work);\n> +\tstruct ice_pf *pf = container_of(dplls, struct ice_pf, dplls);\n> +\tenum ice_e825c_ref_clk clk;\n> +\tbool do_switch;\n> +\n> +\tmutex_lock(&pf->dplls.lock);\n> +\tdo_switch = pf->dplls.txclk_switch_requested;\nTwo stray spaces.\n\n> +\tclk = pf->ptp.port.tx_clk_req;\n> +\tpf->dplls.txclk_switch_requested = false;\nTwo stray spaces.\n\n> +\tmutex_unlock(&pf->dplls.lock);\n> +\n> +\tif (do_switch)\n> +\t\tice_txclk_set_clk(pf, clk);\n> +}\n> +\n\n...\n\n> --\n> 2.39.3","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=CJk5N+ku;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.138; 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