[{"id":3684635,"web_url":"http://patchwork.ozlabs.org/comment/3684635/","msgid":"","list_archive_url":null,"date":"2026-04-30T11:46:54","subject":"Re: [Intel-wired-lan] [PATCH v7 net-next 5/8] ice: introduce TXC\n DPLL device and TX ref clock pin framework for E825","submitter":{"id":75597,"url":"http://patchwork.ozlabs.org/api/people/75597/","name":"Aleksandr Loktionov","email":"aleksandr.loktionov@intel.com"},"content":"> -----Original Message-----\n> From: Intel-wired-lan On Behalf\n> Of Grzegorz Nitka\n> Sent: Thursday, April 30, 2026 11:43 AM\n> To: netdev@vger.kernel.org\n> Cc: Vecera, Ivan ; vadim.fedorenko@linux.dev;\n> kuba@kernel.org; jiri@resnulli.us; edumazet@google.com; Kitszel,\n> Przemyslaw ; richardcochran@gmail.com;\n> donald.hunter@gmail.com; linux-kernel@vger.kernel.org; Kubalewski,\n> Arkadiusz ; andrew+netdev@lunn.ch;\n> intel-wired-lan@lists.osuosl.org; horms@kernel.org;\n> Prathosh.Satish@microchip.com; Nguyen, Anthony L\n> ; pabeni@redhat.com; davem@davemloft.net\n> Subject: [Intel-wired-lan] [PATCH v7 net-next 5/8] ice: introduce TXC\n> DPLL device and TX ref clock pin framework for E825\n> \n> E825 devices provide a dedicated TX clock (TXC) domain which may be\n> driven by multiple reference clock sources, including external board\n> references and port-derived SyncE. To support future TX clock control\n> and observability through the Linux DPLL subsystem, introduce a\n> separate TXC DPLL device (of DPLL_TYPE_GENERIC) and a framework for\n> representing TX reference clock inputs.\n> \n> This change adds a new internal DPLL pin type (TXCLK) and registers TX\n> reference clock pins for E825-based devices:\n> - EXT_EREF0: a board-level external electrical reference\n> - SYNCE: a port-derived SyncE reference described via firmware nodes\n> \n> The TXC DPLL device is created and managed alongside the existing PPS\n> and EEC DPLL instances. TXCLK pins are registered directly or deferred\n> via a notifier when backed by fwnode-described pins.\n> A per-pin attribute encodes the TX reference source associated with\n> each TXCLK pin.\n> \n> At this stage, TXCLK pin state callbacks and TXC DPLL lock status\n> reporting are implemented as placeholders. Pin state getters always\n> return DISCONNECTED, and the TXC DPLL is initialized in the UNLOCKED\n> state. No hardware configuration or TX reference switching is\n> performed yet.\n> \n> This patch establishes the structural groundwork required for\n> hardware-backed TX reference selection, verification, and\n> synchronization status reporting, which will be implemented in\n> subsequent patches.\n> \n> Reviewed-by: Arkadiusz Kubalewski \n> Signed-off-by: Grzegorz Nitka \n> ---\n> drivers/net/ethernet/intel/ice/ice_dpll.c | 296 ++++++++++++++++++-\n> -\n> drivers/net/ethernet/intel/ice/ice_dpll.h | 6 +\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 7 +\n> 3 files changed, 286 insertions(+), 23 deletions(-)\n> \n> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c\n> b/drivers/net/ethernet/intel/ice/ice_dpll.c\n> index 62f75701d652..d839b50187ba 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c\n> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c\n> @@ -19,6 +19,11 @@\n> #define ICE_DPLL_SW_PIN_INPUT_BASE_QSFP\t\t6\n> #define ICE_DPLL_SW_PIN_OUTPUT_BASE\t\t0\n> \n> +#define E825_EXT_EREF_PIN_IDX\t\t\t0\n> +#define E825_EXT_SYNCE_PIN_IDX\t\t\t1\n> +#define E825_RCLK_PARENT_0_PIN_IDX\t\t0\n> +#define E825_RCLK_PARENT_1_PIN_IDX\t\t1\n> +\n> #define ICE_DPLL_PIN_SW_INPUT_ABS(in_idx) \\\n> \t(ICE_DPLL_SW_PIN_INPUT_BASE_SFP + (in_idx))\n> \n> @@ -57,6 +62,7 @@\n> * @ICE_DPLL_PIN_TYPE_OUTPUT: output pin\n> * @ICE_DPLL_PIN_TYPE_RCLK_INPUT: recovery clock input pin\n> * @ICE_DPLL_PIN_TYPE_SOFTWARE: software controlled SMA/U.FL pins\n\n\n...\n\n> /**\n> @@ -3199,19 +3276,40 @@ static bool ice_dpll_is_fwnode_pin(struct\n> ice_dpll_pin *pin)\n> \treturn !IS_ERR_OR_NULL(pin->fwnode);\n> }\n> \n> +static bool ice_dpll_fwnode_eq(const struct fwnode_handle *a,\n> +\t\t\t const struct fwnode_handle *b) {\n> +\treturn a && b && a == b;\nI'm pretty sure that return a && a == b; is enough instead.\n\n\nReviewed-by: Aleksandr Loktionov \n\n> +}\n> +\n\n...\n\n> #define E810C_QSFP_C827_0_HANDLE 2\n> #define E810C_QSFP_C827_1_HANDLE 3\n> \n> --\n> 2.39.3","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=g23WjSeR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; helo=smtp4.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from smtp4.osuosl.org (smtp4.osuosl.org [IPv6:2605:bc80:3010::137])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5spn5F2Fz1yHZ\n\tfor ; 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