[{"id":3684472,"web_url":"http://patchwork.ozlabs.org/comment/3684472/","msgid":"","list_archive_url":null,"date":"2026-04-30T06:45:12","subject":"Re: [PATCH] pinctrl: qcom: Unconditionally mark gpio as wakeup enable","submitter":{"id":90731,"url":"http://patchwork.ozlabs.org/api/people/90731/","name":"Maulik Shah (mkshah)","email":"maulik.shah@oss.qualcomm.com"},"content":"On 4/30/2026 11:24 AM, Sneh Mankad wrote:\n> The wakeup enable bit needs to be set irrespective of the SoC using PDC or\n> MPM as wakeup capable irqchip to allow the GPIO interrupts to be forwarded\n> to parent irqchip.\n> \n> This is set only for PDC irqchip using additional check skip_wake_irqs\n> making it impossible for MPM irqchip to detect the GPIO interrupt during\n> SoC low power mode since for MPM irqchip the skip_wake_irqs is always\n> false.\n> \n> Remove skip_wake_irqs condition when setting wakeup enable bit to allow\n> forwarding GPIO interrupts for SoCs using MPM irqchip too.\n> \n> Fixes: 76b446f5b86e (\"pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits\")\n> Signed-off-by: Sneh Mankad \n> ---\n> drivers/pinctrl/qcom/pinctrl-msm.c | 4 ++--\n> 1 file changed, 2 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c\n> index 45b3a2763eb85405fecdd4770ba3d4ab684563f0..96df8eb8f5d3f3bcfe165ac02a07414e491f1178 100644\n> --- a/drivers/pinctrl/qcom/pinctrl-msm.c\n> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n> @@ -1247,7 +1247,7 @@ static int msm_gpio_irq_reqres(struct irq_data *d)\n> \t * While the name implies only the wakeup event, it's also required for\n> \t * the interrupt event.\n> \t */\n\n\nPasting full comment from driver, since this is not visible in the diff.\n\n /*\n * If the wakeup_enable bit is present and marked as available for the\n * requested GPIO, it should be enabled when the GPIO is marked as\n * wake irq in order to allow the interrupt event to be transfered to\n * the PDC HW.\n * While the name implies only the wakeup event, it's also required for\n * the interrupt event.\n */\n\nCan you update in the above comment also to mention both PDC and MPM HW.\nWhile touching this comment, please also correct spelling typo for transfered.\n\n\"transferred to the PDC/MPM HW.\"\n\nPost this update,\n\nReviewed-by: Maulik Shah \n\nThanks,\nMaulik\n\n> -\tif (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {\n> +\tif (g->intr_wakeup_present_bit) {\n> \t\tu32 intr_cfg;\n> \n> \t\traw_spin_lock_irqsave(&pctrl->lock, flags);\n> @@ -1275,7 +1275,7 @@ static void msm_gpio_irq_relres(struct irq_data *d)\n> \tunsigned long flags;\n> \n> \t/* Disable the wakeup_enable bit if it has been set in msm_gpio_irq_reqres() */\n> -\tif (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {\n> +\tif (g->intr_wakeup_present_bit) {\n> \t\tu32 intr_cfg;\n> \n> \t\traw_spin_lock_irqsave(&pctrl->lock, flags);\n> \n> ---\n> base-commit: b4e07588e743c989499ca24d49e752c074924a9a\n> change-id: 20260430-enable_wakeup_capable_gpios-cb9439ae8772\n> \n> Best regards,","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Ab9JEHLX;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Y8hjnirZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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