[{"id":3684518,"web_url":"http://patchwork.ozlabs.org/comment/3684518/","msgid":"<20260430-adaptable-wonderful-hoatzin-e1056f@quoll>","list_archive_url":null,"date":"2026-04-30T08:04:58","subject":"Re: [PATCH v3 2/3] arm64: dts: imx95: Add dma, intr, aer and pme\n interrupters for pcie{0,1}","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On Thu, Apr 30, 2026 at 01:09:53PM +0800, Richard Zhu wrote:\n> Add dma, intr, aer and pme interrupters for pcie{0,1}.\n> \n> Signed-off-by: Richard Zhu \n> ---\n> arch/arm64/boot/dts/freescale/imx95.dtsi | 16 ++++++++++++----\n> 1 file changed, 12 insertions(+), 4 deletions(-)\n> \n> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi\n> index 71394871d8dd0..6896d9c15bf53 100644\n> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi\n> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi\n> @@ -1861,8 +1861,12 @@ pcie0: pcie@4c300000 {\n> \t\t\tbus-range = <0x00 0xff>;\n> \t\t\tnum-lanes = <1>;\n> \t\t\tnum-viewport = <8>;\n> -\t\t\tinterrupts = ;\n> -\t\t\tinterrupt-names = \"msi\";\n\nWhy there is no fixes tag if this is here for two years and you claim\nthat IT CANNOT work without these interrupts?\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=jrFXUzp9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=utf-8","Content-Disposition":"inline","In-Reply-To":"<20260430050954.3467984-3-hongxing.zhu@nxp.com>"}},{"id":3684541,"web_url":"http://patchwork.ozlabs.org/comment/3684541/","msgid":"","list_archive_url":null,"date":"2026-04-30T08:37:27","subject":"RE: [PATCH v3 2/3] arm64: dts: imx95: Add dma, intr, aer and pme\n interrupters for pcie{0,1}","submitter":{"id":68324,"url":"http://patchwork.ozlabs.org/api/people/68324/","name":"Hongxing Zhu","email":"hongxing.zhu@nxp.com"},"content":"> -----Original Message-----\n> From: Krzysztof Kozlowski \n> Sent: Thursday, April 30, 2026 4:05 PM\n> To: Hongxing Zhu \n> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;\n> bhelgaas@google.com; Frank Li ; l.stach@pengutronix.de;\n> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;\n> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; linux-\n> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;\n> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org\n> Subject: Re: [PATCH v3 2/3] arm64: dts: imx95: Add dma, intr, aer and pme\n> interrupters for pcie{0,1}\n> \n> On Thu, Apr 30, 2026 at 01:09:53PM +0800, Richard Zhu wrote:\n> > Add dma, intr, aer and pme interrupters for pcie{0,1}.\n> >\n> > Signed-off-by: Richard Zhu \n> > ---\n> > arch/arm64/boot/dts/freescale/imx95.dtsi | 16 ++++++++++++----\n> > 1 file changed, 12 insertions(+), 4 deletions(-)\n> >\n> > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi\n> > b/arch/arm64/boot/dts/freescale/imx95.dtsi\n> > index 71394871d8dd0..6896d9c15bf53 100644\n> > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi\n> > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi\n> > @@ -1861,8 +1861,12 @@ pcie0: pcie@4c300000 {\n> > \t\t\tbus-range = <0x00 0xff>;\n> > \t\t\tnum-lanes = <1>;\n> > \t\t\tnum-viewport = <8>;\n> > -\t\t\tinterrupts = ;\n> > -\t\t\tinterrupt-names = \"msi\";\n> \n> Why there is no fixes tag if this is here for two years and you claim that IT\n> CANNOT work without these interrupts?\nRegarding the Fixes tag: I think that it is not needed here because this is not\n a bug fix.\n\nThe driver has been functional for two years using only the MSI interrupt. The\ncurrent implementation works correctly for basic PCIe operation. This patch\nadds support for additional interrupt lines (dma, intr, aer, pme) to enable\nenhanced features and capabilities that were previously not utilized.\n\nThis is a feature enhancement, not a correction of broken functionality. The\nhardware supports these additional interrupts, and we're now exposing them in\nthe device tree to allow the driver to take advantage of enhanced features.\n\nI hope this clarifies your concern.\n\nBest Regards\nRichard Zhu\n> \n> Best regards,\n> Krzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=cLm7mqrk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53454-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com\n header.b=\"cLm7mqrk\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=52.101.72.60","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=nxp.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=nxp.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5nks44QDz1xqf\n\tfor ; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"AM0PR04MB5220.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 76680b5f-6668-45bf-3fe7-08dea693b5a7","X-MS-Exchange-CrossTenant-originalarrivaltime":"30 Apr 2026 08:37:27.0812\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n N7bV7QqWigTcqGfkVXYrIEDjwD7/LAzc1GTEYjmC028U4XAsoorb5a0WoWK9dLjWk9IvtWigvJT6+q1030DlaA==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DBBPR04MB7706"}},{"id":3684602,"web_url":"http://patchwork.ozlabs.org/comment/3684602/","msgid":"<866455eb-5886-4d6a-b384-2cbed18b67b6@kernel.org>","list_archive_url":null,"date":"2026-04-30T10:49:21","subject":"Re: [PATCH v3 2/3] arm64: dts: imx95: Add dma, intr, aer and pme\n interrupters for pcie{0,1}","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On 30/04/2026 10:37, Hongxing Zhu wrote:\n>> -----Original Message-----\n>> From: Krzysztof Kozlowski \n>> Sent: Thursday, April 30, 2026 4:05 PM\n>> To: Hongxing Zhu \n>> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;\n>> bhelgaas@google.com; Frank Li ; l.stach@pengutronix.de;\n>> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;\n>> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; linux-\n>> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;\n>> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org\n>> Subject: Re: [PATCH v3 2/3] arm64: dts: imx95: Add dma, intr, aer and pme\n>> interrupters for pcie{0,1}\n>>\n>> On Thu, Apr 30, 2026 at 01:09:53PM +0800, Richard Zhu wrote:\n>>> Add dma, intr, aer and pme interrupters for pcie{0,1}.\n>>>\n>>> Signed-off-by: Richard Zhu \n>>> ---\n>>> arch/arm64/boot/dts/freescale/imx95.dtsi | 16 ++++++++++++----\n>>> 1 file changed, 12 insertions(+), 4 deletions(-)\n>>>\n>>> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi\n>>> b/arch/arm64/boot/dts/freescale/imx95.dtsi\n>>> index 71394871d8dd0..6896d9c15bf53 100644\n>>> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi\n>>> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi\n>>> @@ -1861,8 +1861,12 @@ pcie0: pcie@4c300000 {\n>>> \t\t\tbus-range = <0x00 0xff>;\n>>> \t\t\tnum-lanes = <1>;\n>>> \t\t\tnum-viewport = <8>;\n>>> -\t\t\tinterrupts = ;\n>>> -\t\t\tinterrupt-names = \"msi\";\n>>\n>> Why there is no fixes tag if this is here for two years and you claim that IT\n>> CANNOT work without these interrupts?\n> Regarding the Fixes tag: I think that it is not needed here because this is not\n> a bug fix.\n> \n> The driver has been functional for two years using only the MSI interrupt. The\n\nThat's not what your binding said. Get your patchset straight including\nproper ABI impact explanations.\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=SS5qTBCr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-53459-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"SS5qTBCr\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5rXC1Fk5z1yHZ\n\tfor ; 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