[{"id":3684515,"web_url":"http://patchwork.ozlabs.org/comment/3684515/","msgid":"<20260430-proud-ammonite-of-gaiety-abaafc@quoll>","list_archive_url":null,"date":"2026-04-30T08:04:14","subject":"Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and\n pme interrupts","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On Thu, Apr 30, 2026 at 01:09:52PM +0800, Richard Zhu wrote:\n> Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe binding\n> to support PCIe event-based interrupts for general controller events,\n> Advanced Error Reporting, and Power Management Events respectively.\n> \n> These interrupts are optional for existing variants (imx6q, imx6sx, imx6qp,\n> imx7d, imx8mq, imx8mm, imx8mp) to maintain backward compatibility with\n> existing device trees.\n> \n> For fsl,imx95-pcie, all 5 interrupts (msi, dma, intr, aer, pme) are\n> mandatory due to hardware requirements.\n> \n> This introduces an ABI requirement for fsl,imx95-pcie. The i.MX95 hardware\n> requires dedicated interrupt lines for AER, PME, and general controller\n> events due to its redesigned interrupt architecture. i.MX95 cannot\n> function correctly without explicit interrupt routing for error handling,\n> power management and link event detection.\n\nfsl,imx95-pcie was added more than two years ago, so how it cannot\nfunction correctly? Are you saying that for two years you had here\ncompletely broken code?\n\nIf this wasn't tested for two years, how can we believe anything is\ntested now?\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=hYt0iBLS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53450-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"hYt0iBLS\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5mt12QZgz1yHZ\n\tfor ; Thu, 30 Apr 2026 18:04:41 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id BB3E63020AA3\n\tfor ; Thu, 30 Apr 2026 08:04:18 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 05D0638E5EF;\n\tThu, 30 Apr 2026 08:04:18 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id CD6F525A2A4;\n\tThu, 30 Apr 2026 08:04:17 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id D4B95C2BCB3;\n\tThu, 30 Apr 2026 08:04:16 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777536257; cv=none;\n b=E5Dilk7dsKRVGbrNPj5zVTCinFMVj4LxmONR6kbQyKaVpUfftbwBc4D+erQOcEKCOLU6BC3Zkr74ZEF8panAsH1RfHncBKNfKHs/+F7//QsxUWkShQAb1wUdIRlTRx621YYb4uD7KTZcMsnpdeP8A6bkXTfWdeuQlUl9JvaiXV4=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777536257; c=relaxed/simple;\n\tbh=/YKW9Bgtg7TEVcVmic3y5cqQ+hd1ttAg/W7NjZNPROs=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=MXrJkiQX2v/KU4FRGYQ3/p/yBdTkCPsl76Gbx9K/51bnDeXC0F6VX7KKeL0Tr/c4Mjm4yipGlrI6LhU8fL6A5pPNb3PbVSykpi2YAG1a4hay7YFnFBgkqZSwq938AMUFu8SJ/U9/Nzhg5p0vhvr8yzyhhqkrHByw7xHAFdBLATo=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=hYt0iBLS; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777536257;\n\tbh=/YKW9Bgtg7TEVcVmic3y5cqQ+hd1ttAg/W7NjZNPROs=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=hYt0iBLSRZ8rOZbYkE1Ds6rZZnZuItlYW/Ux+0iSuJvZLfdZPuI30RVOQeibKRjpj\n\t tvkrAY8kZhBnKhMSrEkGUqBB3+LVaGr4MC/5BXgrA4UxOV6cnMVDeMiq/omyfU1xQg\n\t YGPIFdWKrvJQ/FbhJILEpT4ryXpOQ8YDHOR7AYRP4w2HZNoLW94W0iEGJDcf+g49Ai\n\t X4XPgpbPFu7taGYLabuCVflJ1C0M/dMej4MBpmm1OCOlc4kZDX7RKIxyrO8IIpFu5b\n\t aiNaQ37aY8SO9xGDosunJyXoffj+B8pjs3Skv0gbd5tR8eODNqEWpI32NSSIYVzt+W\n\t 3E9FZGvM4iL9Q==","Date":"Thu, 30 Apr 2026 10:04:14 +0200","From":"Krzysztof Kozlowski ","To":"Richard Zhu ","Cc":"robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,\n\tbhelgaas@google.com, frank.li@nxp.com, l.stach@pengutronix.de,\n lpieralisi@kernel.org,\n\tkwilczynski@kernel.org, mani@kernel.org, s.hauer@pengutronix.de,\n kernel@pengutronix.de,\n\tfestevam@gmail.com, linux-pci@vger.kernel.org,\n linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and\n pme interrupts","Message-ID":"<20260430-proud-ammonite-of-gaiety-abaafc@quoll>","References":"<20260430050954.3467984-1-hongxing.zhu@nxp.com>\n <20260430050954.3467984-2-hongxing.zhu@nxp.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","In-Reply-To":"<20260430050954.3467984-2-hongxing.zhu@nxp.com>"}},{"id":3684535,"web_url":"http://patchwork.ozlabs.org/comment/3684535/","msgid":"","list_archive_url":null,"date":"2026-04-30T08:37:19","subject":"RE: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and\n pme interrupts","submitter":{"id":68324,"url":"http://patchwork.ozlabs.org/api/people/68324/","name":"Hongxing Zhu","email":"hongxing.zhu@nxp.com"},"content":"> -----Original Message-----\n> From: Krzysztof Kozlowski \n> Sent: Thursday, April 30, 2026 4:04 PM\n> To: Hongxing Zhu \n> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;\n> bhelgaas@google.com; Frank Li ; l.stach@pengutronix.de;\n> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;\n> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; linux-\n> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;\n> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org\n> Subject: Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme\n> interrupts\n> \n> On Thu, Apr 30, 2026 at 01:09:52PM +0800, Richard Zhu wrote:\n> > Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe\n> > binding to support PCIe event-based interrupts for general controller\n> > events, Advanced Error Reporting, and Power Management Events respectively.\n> >\n> > These interrupts are optional for existing variants (imx6q, imx6sx,\n> > imx6qp, imx7d, imx8mq, imx8mm, imx8mp) to maintain backward\n> > compatibility with existing device trees.\n> >\n> > For fsl,imx95-pcie, all 5 interrupts (msi, dma, intr, aer, pme) are\n> > mandatory due to hardware requirements.\n> >\n> > This introduces an ABI requirement for fsl,imx95-pcie. The i.MX95\n> > hardware requires dedicated interrupt lines for AER, PME, and general\n> > controller events due to its redesigned interrupt architecture. i.MX95\n> > cannot function correctly without explicit interrupt routing for error\n> > handling, power management and link event detection.\n> \n> fsl,imx95-pcie was added more than two years ago, so how it cannot function\n> correctly? Are you saying that for two years you had here completely broken\n> code?\n>\n> If this wasn't tested for two years, how can we believe anything is tested now?\nThe basic PCIe functionality has been working since the initial fsl,imx95-pcie\nsupport. However, AER (Advanced Error Reporting) and link up/down detection\nwere not previously enabled. This patch-set adds and verifies support for\nthese advanced features.\n\nBest Regards\nRichard Zhu\n> \n> Best regards,\n> Krzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=WHiZXoZL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-53453-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com\n header.b=\"WHiZXoZL\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.130.21","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=nxp.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=nxp.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5nbt1Qqlz1yGq\n\tfor ; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"AM0PR04MB5220.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 44338471-0e2b-4236-4168-08dea693b150","X-MS-Exchange-CrossTenant-originalarrivaltime":"30 Apr 2026 08:37:19.7823\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n oMJn1/vHZpKSqk7dxfZomftjgRjSP+QhZoQypZup3qTM87m9sAy1IHxOpuesj6EAnxsY8IVmSCxkxCWoB5JE+w==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DBBPR04MB7706"}},{"id":3684603,"web_url":"http://patchwork.ozlabs.org/comment/3684603/","msgid":"<55258a51-9cdb-451c-be06-74b9b3020cbc@kernel.org>","list_archive_url":null,"date":"2026-04-30T10:48:35","subject":"Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and\n pme interrupts","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On 30/04/2026 10:37, Hongxing Zhu wrote:\n>> -----Original Message-----\n>> From: Krzysztof Kozlowski \n>> Sent: Thursday, April 30, 2026 4:04 PM\n>> To: Hongxing Zhu \n>> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;\n>> bhelgaas@google.com; Frank Li ; l.stach@pengutronix.de;\n>> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;\n>> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; linux-\n>> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;\n>> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org\n>> Subject: Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme\n>> interrupts\n>>\n>> On Thu, Apr 30, 2026 at 01:09:52PM +0800, Richard Zhu wrote:\n>>> Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe\n>>> binding to support PCIe event-based interrupts for general controller\n>>> events, Advanced Error Reporting, and Power Management Events respectively.\n>>>\n>>> These interrupts are optional for existing variants (imx6q, imx6sx,\n>>> imx6qp, imx7d, imx8mq, imx8mm, imx8mp) to maintain backward\n>>> compatibility with existing device trees.\n>>>\n>>> For fsl,imx95-pcie, all 5 interrupts (msi, dma, intr, aer, pme) are\n>>> mandatory due to hardware requirements.\n>>>\n>>> This introduces an ABI requirement for fsl,imx95-pcie. The i.MX95\n>>> hardware requires dedicated interrupt lines for AER, PME, and general\n>>> controller events due to its redesigned interrupt architecture. i.MX95\n>>> cannot function correctly without explicit interrupt routing for error\n>>> handling, power management and link event detection.\n>>\n>> fsl,imx95-pcie was added more than two years ago, so how it cannot function\n>> correctly? Are you saying that for two years you had here completely broken\n>> code?\n>>\n>> If this wasn't tested for two years, how can we believe anything is tested now?\n> The basic PCIe functionality has been working since the initial fsl,imx95-pcie\n> support. However, AER (Advanced Error Reporting) and link up/down detection\n> were not previously enabled. This patch-set adds and verifies support for\n> these advanced features.\n> \n\nThat is not what you said in the commit msg.\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=bhOE8ONC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53458-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"bhOE8ONC\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5rYc5XHTz1yGq\n\tfor ; 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