[{"id":3684282,"web_url":"http://patchwork.ozlabs.org/comment/3684282/","msgid":"","list_archive_url":null,"date":"2026-04-29T21:33:00","subject":"Re: [PATCH 2/2] target/or1k: fix gen_div INT_MIN / -1 undefined\n behavior","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/30/26 03:03, joel--- via qemu development wrote:\n> From: Joel Holdsworth \n> \n> Signed division of INT_MIN (0x80000000) by -1 produces a result that\n> overflows a 32-bit signed integer. On many host architectures (x86,\n> ARM) this triggers a hardware exception. The existing code only guards\n> against divide-by-zero but not this case.\n> \n> Add an explicit check for the INT_MIN / -1 pattern and suppress the\n> host-side exception by substituting a divisor of 1, setting the\n> overflow flag instead.\n> \n> Signed-off-by: Joel Holdsworth \n> ---\n> target/or1k/translate.c | 22 ++++++++++++++++++----\n> 1 file changed, 18 insertions(+), 4 deletions(-)\n> \n> diff --git a/target/or1k/translate.c b/target/or1k/translate.c\n> index 1602e204fe..68d40111f0 100644\n> --- a/target/or1k/translate.c\n> +++ b/target/or1k/translate.c\n> @@ -279,13 +279,27 @@ static void gen_div(DisasContext *dc, TCGv_i32 dest,\n> TCGv_i32 srca, TCGv_i32 srcb)\n> {\n> TCGv_i32 t0 = tcg_temp_new_i32();\n> + TCGv_i32 ov = tcg_temp_new_i32();\n> \n> - tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_ov, srcb, 0);\n> - /* The result of divide-by-zero is undefined.\n> - Suppress the host-side exception by dividing by 1. */\n> - tcg_gen_or_i32(t0, srcb, cpu_sr_ov);\n> + /* Check for divide-by-zero. */\n> + tcg_gen_setcondi_i32(TCG_COND_EQ, ov, srcb, 0);\n> +\n> + /* Check for INT_MIN / -1 overflow (0x80000000 / -1). */\n> + TCGv_i32 t_is_min = tcg_temp_new_i32();\n> + TCGv_i32 t_is_neg1 = tcg_temp_new_i32();\n> + TCGv_i32 t_intmin_ov = tcg_temp_new_i32();\n> +\n> + tcg_gen_setcondi_i32(TCG_COND_EQ, t_is_min, srca, (int32_t)0x80000000);\n\nJust use INT32_MIN here.\n\n> + tcg_gen_setcondi_i32(TCG_COND_EQ, t_is_neg1, srcb, -1);\n> + tcg_gen_and_i32(t_intmin_ov, t_is_min, t_is_neg1);\n> + tcg_gen_or_i32(ov, ov, t_intmin_ov);\n> +\n> + /* Suppress the host-side exception by dividing by 1 on overflow. */\n> + tcg_gen_movcond_i32(TCG_COND_NE, t0, ov, tcg_constant_i32(0),\n> + tcg_constant_i32(1), srcb);\n> tcg_gen_div_i32(dest, srca, t0);\n> \n> + tcg_gen_mov_i32(cpu_sr_ov, ov);\n> tcg_gen_neg_i32(cpu_sr_ov, cpu_sr_ov);\n> gen_ove_ov(dc);\n> }\n\nIt doesn't make much difference, but you can write this without adding new temps, \nespecially since you don't need to avoid cpu_sr_ov like you're doing.\n\n /* Check for INT_MIN / -1 overflow */\n tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_ov, srca, INT_MIN);\n tcg_gen_setcondi_i32(TCG_COND_EQ, t0, srcb, -1);\n tcg_gen_and_i32(cpu_sr_ov, cpu_sr_ov, t0);\n\n /* Check for divide-by-zero. */\n tcg_gen_setcondi_i32(TCG_COND_EQ, t0, srcb, 0);\n tcg_gen_or_i32(cpu_sr_ov, cpu_sr_ov, t0);\n\n /* Suppress the host-side exception by dividing by 1 on overflow. */\n tcg_gen_movcond_i32(TCG_COND_NE, t0, cpu_sr_ov, tcg_constant_i32(0),\n tcg_constant_i32(1), srcb);\n tcg_gen_div_i32(dest, srca, t0);\n\n tcg_gen_neg_i32(cpu_sr_ov, cpu_sr_ov);\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=LRkvn0Ki;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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