[{"id":3684522,"web_url":"http://patchwork.ozlabs.org/comment/3684522/","msgid":"<844465c2-a78e-438b-adfa-0d059635da58@linux.ibm.com>","list_archive_url":null,"date":"2026-04-30T08:13:30","subject":"Re: [PATCH] rs6000: Builtins for ECC cryptography instructions\n [RFC02669]","submitter":{"id":88474,"url":"http://patchwork.ozlabs.org/api/people/88474/","name":"Surya Kumari Jangala","email":"jskumari@linux.ibm.com"},"content":"Hi,\n\nOn 30/04/26 12:01 AM, Manjunath S Matti wrote:\n> This patch depends on the -mcpu=future infrastructure.\n> The changes have been bootstrapped and regression tested\n> on powerpc64le-linux.\n\nThe commit message should be 72 chars in length. Please format accordingly.\n\n> \n> This patch implements builtin support for 21 new ECC (Elliptic\n> Curve Cryptography) acceleration instructions defined in\n> RFC02669 for Power ISA v3.2. These instructions are designed\n\nThe next ISA version number has not yet been finalized. So pls use\n'future ISA' instead of 3.2\n\n> to accelerate P-256 and P-384 elliptic curve operations on\n> POWER future processors. These instructions may or may not\n> be supported in a future processor. Note, the names of the\n> builtins may change in future.\n> \n> The instructions are organized into five categories:\n> \n> 1. Multiply-Multiply operations (3 instructions):\n>    - xxmulmul: Multiply-multiply with scaling (scale values 0-6)\n>    - xxmulmulhiadd: Multiply-multiply with high add and accumulator\n>    - xxmulmulloadd: Multiply-multiply low add with accumulator\n> \n> 2. Scaled Multiply-Sum operations (3 instructions):\n>    - xxssumudm: Scaled sum unsigned doubleword modulo\n>    - xxssumudmc: Scaled sum unsigned doubleword modulo carry\n>    - xxssumudmcext: Extended version with separate accumulator\n>      (prefixed)\n> \n> 3. Quadword Add/Subtract operations (4 instructions):\n>    - xsaddadduqm: Add add unsigned quadword modulo\n>    - xsaddaddsuqm: Add add scaled unsigned quadword modulo\n>    - xsaddsubuqm: Add subtract unsigned quadword modulo\n>    - xsaddsubsuqm: Add subtract scaled unsigned quadword modulo\n> \n> 4. Merge operations (4 instructions):\n>    - xsmerge2t1uqm, xsmerge2t2uqm, xsmerge2t3uqm: 2-operand merge\n>    - xsmerge3t1uqm: 3-operand merge with accumulator\n> \n> 5. Rebase operations (7 instructions):\n>    - xsrebase2t1uqm through xsrebase2t4uqm: 2-operand rebase\n>    - xsrebase3t1uqm through xsrebase3t3uqm: 3-operand rebase with\n>      accumulator\n> \n> All instructions operate on 128-bit unsigned integers\n> (vector unsigned __int128) and use VSX registers.\n> The xxssumudmcext instruction is a prefixed instruction (8 bytes),\n> while all others use the standard XX3 form (4 bytes).\n> \n> 2026-04-29 Manjunath Matti <mmatti@linux.ibm.com>\n> \n> gcc/ChangeLog:\n>       * config/rs6000/predicates.md (const_0_to_6_operand): New\n> \tpredicate for xxmulmul scale field validation.\n\nJust 'new predicate' is enough.\n\n>       * config/rs6000/rs6000-builtins.def: Add 21 ECC builtin\n\nList down all the builtin names.\n\n> \tdefinitions under [future] stanza.\n>       * config/rs6000/vsx.md: Add UNSPEC constants for ECC instructions.\n\nList down all the UNSPECs.\n\n> \tAdd 21 instruction patterns with appropriate attributes.\n\nAnd the instruction patterns too.\n\n>       * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add\n> \tdocumentation for ECC cryptography builtins available on\n> \tISA 3.2.\n\nRemove 3.2.\n\n> \n> gcc/testsuite/ChangeLog:\n>       * gcc.target/powerpc/ecc-builtin-1.c: New test for ECC builtins.\n> \n> diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md\n> index 54dbc8bcc95..4162c22f8f6 100644\n> --- a/gcc/config/rs6000/predicates.md\n> +++ b/gcc/config/rs6000/predicates.md\n> @@ -312,6 +312,11 @@\n>    (and (match_code \"const_int\")\n>         (match_test \"IN_RANGE (INTVAL (op), 2, 3)\")))\n>  \n> +;; Match op = 0..6.\n> +(define_predicate \"const_0_to_6_operand\"\n> +  (and (match_code \"const_int\")\n> +       (match_test \"IN_RANGE (INTVAL (op), 0, 6)\")))\n> +\n>  ;; Match op = 0..7.\n>  (define_predicate \"const_0_to_7_operand\"\n>    (and (match_code \"const_int\")\n> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def\n> index 7e5a4fb96e7..0c62872b62f 100644\n> --- a/gcc/config/rs6000/rs6000-builtins.def\n> +++ b/gcc/config/rs6000/rs6000-builtins.def\n> @@ -3924,3 +3924,72 @@\n>  \n>    void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);\n>      STXVP nothing {mma,pair}\n> +\n> +\n> +; ECC (Elliptic Curve Cryptography) acceleration instructions for Power future.\n> +; These instructions support P-256 and P-384 elliptic curve operations.\n> +[future]\n> +  const vuq __builtin_vsx_xxmulmul (vull, vull, const int<0,6>);\n> +    XXMULMUL vsx_xxmulmul {}\n> +\n> +  const vuq __builtin_vsx_xxmulmulhiadd (vuq, vull, vull, const int<1>, \\\n> +                                          const int<1>, const int<1>);\n> +    XXMULMULHIADD vsx_xxmulmulhiadd {}\n> +\n> +  const vuq __builtin_vsx_xxmulmulloadd (vuq, vull, vull, const int<1>, \\\n> +                                          const int<1>);\n> +    XXMULMULLOADD vsx_xxmulmulloadd {}\n> +\n> +  const vuq __builtin_vsx_xxssumudm (vull, vull, const int<1>);\n> +    XXSSUMUDM vsx_xxssumudm {}\n> +\n> +  const vuq __builtin_vsx_xxssumudmc (vull, vull, const int<1>);\n> +    XXSSUMUDMC vsx_xxssumudmc {}\n> +\n> +  const vuq __builtin_vsx_xxssumudmcext (vull, vull, vuq, const int<1>);\n> +    XXSSUMUDMCEXT vsx_xxssumudmcext {}\n> +\n> +  const vuq __builtin_vsx_xsaddadduqm (vuq, vuq, vuq);\n> +    XSADDADDUQM vsx_xsaddadduqm {}\n> +\n> +  const vuq __builtin_vsx_xsaddaddsuqm (vuq, vuq, vuq);\n> +    XSADDADDSUQM vsx_xsaddaddsuqm {}\n> +\n> +  const vuq __builtin_vsx_xsaddsubuqm (vuq, vuq, vuq);\n> +    XSADDSUBUQM vsx_xsaddsubuqm {}\n> +\n> +  const vuq __builtin_vsx_xsaddsubsuqm (vuq, vuq, vuq);\n> +    XSADDSUBSUQM vsx_xsaddsubsuqm {}\n> +\n> +  const vuq __builtin_vsx_xsmerge2t1uqm (vuq, vuq);\n> +    XSMERGE2T1UQM vsx_xsmerge2t1uqm {}\n> +\n> +  const vuq __builtin_vsx_xsmerge2t2uqm (vuq, vuq);\n> +    XSMERGE2T2UQM vsx_xsmerge2t2uqm {}\n> +\n> +  const vuq __builtin_vsx_xsmerge2t3uqm (vuq, vuq);\n> +    XSMERGE2T3UQM vsx_xsmerge2t3uqm {}\n> +\n> +  const vuq __builtin_vsx_xsmerge3t1uqm (vuq, vuq, vuq);\n> +    XSMERGE3T1UQM vsx_xsmerge3t1uqm {}\n> +\n> +  const vuq __builtin_vsx_xsrebase2t1uqm (vuq, vuq);\n> +    XSREBASE2T1UQM vsx_xsrebase2t1uqm {}\n> +\n> +  const vuq __builtin_vsx_xsrebase2t2uqm (vuq, vuq);\n> +    XSREBASE2T2UQM vsx_xsrebase2t2uqm {}\n> +\n> +  const vuq __builtin_vsx_xsrebase2t3uqm (vuq, vuq);\n> +    XSREBASE2T3UQM vsx_xsrebase2t3uqm {}\n> +\n> +  const vuq __builtin_vsx_xsrebase2t4uqm (vuq, vuq);\n> +    XSREBASE2T4UQM vsx_xsrebase2t4uqm {}\n> +\n> +  const vuq __builtin_vsx_xsrebase3t1uqm (vuq, vuq, vuq);\n> +    XSREBASE3T1UQM vsx_xsrebase3t1uqm {}\n> +\n> +  const vuq __builtin_vsx_xsrebase3t2uqm (vuq, vuq, vuq);\n> +    XSREBASE3T2UQM vsx_xsrebase3t2uqm {}\n> +\n> +  const vuq __builtin_vsx_xsrebase3t3uqm (vuq, vuq, vuq);\n> +    XSREBASE3T3UQM vsx_xsrebase3t3uqm {}\n> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\n> index cfad9b8c6d5..5351535f46a 100644\n> --- a/gcc/config/rs6000/vsx.md\n> +++ b/gcc/config/rs6000/vsx.md\n> @@ -369,6 +369,27 @@\n>     UNSPEC_XXSPLTI32DX\n>     UNSPEC_XXBLEND\n>     UNSPEC_XXPERMX\n> +   UNSPEC_XXMULMUL\n> +   UNSPEC_XXMULMULHIADD\n> +   UNSPEC_XXMULMULLOADD\n> +   UNSPEC_XXSSUMUDM\n> +   UNSPEC_XXSSUMUDMC\n> +   UNSPEC_XXSSUMUDMCEXT\n> +   UNSPEC_XSADDADDUQM\n> +   UNSPEC_XSADDADDSUQM\n> +   UNSPEC_XSADDSUBUQM\n> +   UNSPEC_XSADDSUBSUQM\n> +   UNSPEC_XSMERGE2T1UQM\n> +   UNSPEC_XSMERGE2T2UQM\n> +   UNSPEC_XSMERGE2T3UQM\n> +   UNSPEC_XSMERGE3T1UQM\n> +   UNSPEC_XSREBASE2T1UQM\n> +   UNSPEC_XSREBASE2T2UQM\n> +   UNSPEC_XSREBASE2T3UQM\n> +   UNSPEC_XSREBASE2T4UQM\n> +   UNSPEC_XSREBASE3T1UQM\n> +   UNSPEC_XSREBASE3T2UQM\n> +   UNSPEC_XSREBASE3T3UQM\n>    ])\n>  \n>  (define_int_iterator XVCVBF16\t[UNSPEC_VSX_XVCVSPBF16\n> @@ -6807,3 +6828,259 @@\n>    emit_insn (gen_vsx_extract_v2di (dest_op1, src_op, const1_rtx));\n>    DONE;\n>  })\n> +\n> +\n> +;; ECC (Elliptic Curve Cryptography) acceleration instructions for Power future\n> +;; These instructions support P-256 and P-384 elliptic curve operations\n> +\n> +;; xxmulmul - Multiply-Multiply with scaling\n> +(define_insn \"vsx_xxmulmul\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V2DI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:SI 3 \"const_0_to_6_operand\" \"n\")]\n> +\t\t     UNSPEC_XXMULMUL))]\n> +  \"TARGET_FUTURE\"\n> +  \"xxmulmul %x0,%x1,%x2,%3\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n\nset_attr \"size\" indicates the size of the instruction in bytes. 128 is incorrect here.\n\n> +\n> +;; xxmulmulhiadd - Multiply-Multiply with high add and accumulator\n> +(define_insn \"vsx_xxmulmulhiadd\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V2DI 3 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:SI 4 \"const_0_to_1_operand\" \"n\")\n> +\t\t      (match_operand:SI 5 \"const_0_to_1_operand\" \"n\")\n> +\t\t      (match_operand:SI 6 \"const_0_to_1_operand\" \"n\")]\n> +\t\t     UNSPEC_XXMULMULHIADD))]\n> +  \"TARGET_FUTURE\"\n> +  \"xxmulmulhiadd %x0,%x2,%x3,%4,%5,%6\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xxmulmulloadd - Multiply-Multiply low add with accumulator\n> +(define_insn \"vsx_xxmulmulloadd\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V2DI 3 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:SI 4 \"const_0_to_1_operand\" \"n\")\n> +\t\t      (match_operand:SI 5 \"const_0_to_1_operand\" \"n\")]\n> +\t\t     UNSPEC_XXMULMULLOADD))]\n> +  \"TARGET_FUTURE\"\n> +  \"xxmulmulloadd %x0,%x2,%x3,%4,%5\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xxssumudm - Scaled sum unsigned doubleword modulo\n> +(define_insn \"vsx_xxssumudm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V2DI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:SI 3 \"const_0_to_1_operand\" \"n\")]\n> +\t\t     UNSPEC_XXSSUMUDM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xxssumudm %x0,%x1,%x2,%3\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xxssumudmc - Scaled sum unsigned doubleword modulo carry\n> +(define_insn \"vsx_xxssumudmc\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V2DI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:SI 3 \"const_0_to_1_operand\" \"n\")]\n> +\t\t     UNSPEC_XXSSUMUDMC))]\n> +  \"TARGET_FUTURE\"\n> +  \"xxssumudmc %x0,%x1,%x2,%3\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xxssumudmcext - Scaled sum unsigned doubleword modulo carry extended (prefixed)\n> +(define_insn \"vsx_xxssumudmcext\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V2DI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:SI 4 \"const_0_to_1_operand\" \"n\")]\n> +\t\t     UNSPEC_XXSSUMUDMCEXT))]\n> +  \"TARGET_FUTURE\"\n> +  \"xxssumudmcext %x0,%x1,%x2,%x3,%4\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")\n> +   (set_attr \"length\" \"8\")])\n> +\n> +;; xsaddadduqm - Add add unsigned quadword modulo\n> +(define_insn \"vsx_xsaddadduqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSADDADDUQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsaddadduqm %x0,%x2,%x3\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsaddaddsuqm - Add add scaled unsigned quadword modulo\n> +(define_insn \"vsx_xsaddaddsuqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSADDADDSUQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsaddaddsuqm %x0,%x2,%x3\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsaddsubuqm - Add subtract unsigned quadword modulo\n> +(define_insn \"vsx_xsaddsubuqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSADDSUBUQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsaddsubuqm %x0,%x2,%x3\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsaddsubsuqm - Add subtract scaled unsigned quadword modulo\n> +(define_insn \"vsx_xsaddsubsuqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSADDSUBSUQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsaddsubsuqm %x0,%x2,%x3\"\n> +  [(set_attr \"type\" \"veccomplex\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsmerge2t1uqm - Merge type 1 (2-operand)\n> +(define_insn \"vsx_xsmerge2t1uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSMERGE2T1UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsmerge2t1uqm %x0,%x1,%x2\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsmerge2t2uqm - Merge type 2 (2-operand)\n> +(define_insn \"vsx_xsmerge2t2uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSMERGE2T2UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsmerge2t2uqm %x0,%x1,%x2\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsmerge2t3uqm - Merge type 3 (2-operand)\n> +(define_insn \"vsx_xsmerge2t3uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSMERGE2T3UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsmerge2t3uqm %x0,%x1,%x2\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsmerge3t1uqm - Merge type 1 (3-operand with accumulator)\n> +(define_insn \"vsx_xsmerge3t1uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSMERGE3T1UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsmerge3t1uqm %x0,%x2,%x3\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsrebase2t1uqm - Rebase type 1 (2-operand)\n> +(define_insn \"vsx_xsrebase2t1uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSREBASE2T1UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsrebase2t1uqm %x0,%x1,%x2\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsrebase2t2uqm - Rebase type 2 (2-operand)\n> +(define_insn \"vsx_xsrebase2t2uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSREBASE2T2UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsrebase2t2uqm %x0,%x1,%x2\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsrebase2t3uqm - Rebase type 3 (2-operand)\n> +(define_insn \"vsx_xsrebase2t3uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSREBASE2T3UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsrebase2t3uqm %x0,%x1,%x2\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsrebase2t4uqm - Rebase type 4 (2-operand)\n> +(define_insn \"vsx_xsrebase2t4uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSREBASE2T4UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsrebase2t4uqm %x0,%x1,%x2\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsrebase3t1uqm - Rebase type 1 (3-operand with accumulator)\n> +(define_insn \"vsx_xsrebase3t1uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSREBASE3T1UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsrebase3t1uqm %x0,%x2,%x3\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsrebase3t2uqm - Rebase type 2 (3-operand with accumulator)\n> +(define_insn \"vsx_xsrebase3t2uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSREBASE3T2UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsrebase3t2uqm %x0,%x2,%x3\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> +\n> +;; xsrebase3t3uqm - Rebase type 3 (3-operand with accumulator)\n> +(define_insn \"vsx_xsrebase3t3uqm\"\n> +  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n> +\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n> +\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n> +\t\t     UNSPEC_XSREBASE3T3UQM))]\n> +  \"TARGET_FUTURE\"\n> +  \"xsrebase3t3uqm %x0,%x2,%x3\"\n> +  [(set_attr \"type\" \"vecperm\")\n> +   (set_attr \"size\" \"128\")])\n> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\n> index 0faa5323ce1..4615fa74fae 100644\n> --- a/gcc/doc/extend.texi\n> +++ b/gcc/doc/extend.texi\n> @@ -24696,6 +24696,7 @@ The PVIPR documents the following overloaded functions:\n>  * PowerPC AltiVec Built-in Functions Available on ISA 2.07::\n>  * PowerPC AltiVec Built-in Functions Available on ISA 3.0::\n>  * PowerPC AltiVec Built-in Functions Available on ISA 3.1::\n> +* PowerPC AltiVec Built-in Functions Available on ISA 3.2 (Future)::\n\nRemove 3.2 here and everywhere else it is mentioned.\n\n>  @end menu\n>  \n>  @node PowerPC AltiVec Built-in Functions on ISA 2.05\n> @@ -26729,6 +26730,268 @@ vector unsigned char);\n>  vector unsigned char);\n>  @end smallexample\n>  \n> +@node PowerPC AltiVec Built-in Functions Available on ISA 3.2 (Future)\n> +@subsubsection PowerPC AltiVec Built-in Functions Available on ISA 3.2 (Future)\n\nRename as: \nPowerPC AltiVec/VSX Built-in Functions Available on Future ISA\n\n> +\n> +The following additional built-in functions are available for the\n> +PowerPC family of processors, starting with ISA 3.2 (@option{-mcpu=future}).\n> +These instructions provide hardware acceleration for Elliptic Curve\n> +Cryptography (ECC) operations, specifically optimized for P-256 and P-384\n> +elliptic curves.\n> +\n> +All ECC built-in functions operate on 128-bit unsigned integers\n> +(@code{vector unsigned __int128}) and use VSX registers. The functions\n> +are organized into five categories: multiply-multiply operations, scaled\n> +multiply-sum operations, quadword add/subtract operations, merge operations,\n> +and rebase operations.\n> +\n> +@subsubheading Multiply-Multiply Operations\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xxmulmul (vector unsigned long long @var{a},\n> +                        vector unsigned long long @var{b},\n> +                        const int @var{scale});\n> +@end smallexample\n> +@findex __builtin_vsx_xxmulmul\n> +\n> +Perform a multiply-multiply operation with scaling. The @var{scale} parameter\n> +must be a literal integer value between 0 and 6 inclusive. This instruction\n> +multiplies elements from vectors @var{a} and @var{b} and applies the specified\n> +scaling factor, producing a 128-bit result.\n\nDescription is not needed for these builtins. Since these builtins generate only\none instruction, and since the ISA document will have more thorough information,\njust list down the names of the builtins similar to MMA builtins as listed here:\nhttps://gcc.gnu.org/onlinedocs/gcc//PowerPC-Matrix-Multiply-Assist-Built-in-Functions.html\n\n-Surya\n\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xxmulmulhiadd (vector unsigned __int128 @var{acc},\n> +                             vector unsigned long long @var{a},\n> +                             vector unsigned long long @var{b},\n> +                             const int @var{m1},\n> +                             const int @var{m2},\n> +                             const int @var{m3});\n> +@end smallexample\n> +@findex __builtin_vsx_xxmulmulhiadd\n> +\n> +Perform a multiply-multiply operation with high add and accumulator. The\n> +accumulator @var{acc} is updated with the result. The @var{m1}, @var{m2},\n> +and @var{m3} parameters must be literal integer values of 0 or 1, controlling\n> +the operation mode.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xxmulmulloadd (vector unsigned __int128 @var{acc},\n> +                             vector unsigned long long @var{a},\n> +                             vector unsigned long long @var{b},\n> +                             const int @var{m1},\n> +                             const int @var{m2});\n> +@end smallexample\n> +@findex __builtin_vsx_xxmulmulloadd\n> +\n> +Perform a multiply-multiply low add operation with accumulator. The\n> +accumulator @var{acc} is updated with the result. The @var{m1} and @var{m2}\n> +parameters must be literal integer values of 0 or 1, controlling the\n> +operation mode.\n> +\n> +@subsubheading Scaled Multiply-Sum Operations\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xxssumudm (vector unsigned long long @var{a},\n> +                         vector unsigned long long @var{b},\n> +                         const int @var{scale});\n> +@end smallexample\n> +@findex __builtin_vsx_xxssumudm\n> +\n> +Perform a scaled sum of unsigned doubleword elements modulo 2^128. The\n> +@var{scale} parameter must be a literal integer value of 0 or 1.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xxssumudmc (vector unsigned long long @var{a},\n> +                          vector unsigned long long @var{b},\n> +                          const int @var{scale});\n> +@end smallexample\n> +@findex __builtin_vsx_xxssumudmc\n> +\n> +Perform a scaled sum of unsigned doubleword elements modulo 2^128 with carry\n> +output. The @var{scale} parameter must be a literal integer value of 0 or 1.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xxssumudmcext (vector unsigned long long @var{a},\n> +                             vector unsigned long long @var{b},\n> +                             vector unsigned __int128 @var{c},\n> +                             const int @var{scale});\n> +@end smallexample\n> +@findex __builtin_vsx_xxssumudmcext\n> +\n> +Perform an extended scaled sum of unsigned doubleword elements with a separate\n> +accumulator @var{c}. The @var{scale} parameter must be a literal integer value\n> +of 0 or 1. This is a prefixed instruction (8 bytes).\n> +\n> +@subsubheading Quadword Add/Subtract Operations\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsaddadduqm (vector unsigned __int128 @var{acc},\n> +                           vector unsigned __int128 @var{a},\n> +                           vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsaddadduqm\n> +\n> +Add two unsigned quadword values @var{a} and @var{b}, then add the result\n> +to the accumulator @var{acc}, performing all operations modulo 2^128.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsaddaddsuqm (vector unsigned __int128 @var{acc},\n> +                            vector unsigned __int128 @var{a},\n> +                            vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsaddaddsuqm\n> +\n> +Add two unsigned quadword values @var{a} and @var{b} with scaling, then add\n> +the result to the accumulator @var{acc}, performing all operations modulo 2^128.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsaddsubuqm (vector unsigned __int128 @var{acc},\n> +                           vector unsigned __int128 @var{a},\n> +                           vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsaddsubuqm\n> +\n> +Subtract unsigned quadword @var{b} from @var{a}, then add the result to the\n> +accumulator @var{acc}, performing all operations modulo 2^128.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsaddsubsuqm (vector unsigned __int128 @var{acc},\n> +                            vector unsigned __int128 @var{a},\n> +                            vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsaddsubsuqm\n> +\n> +Subtract unsigned quadword @var{b} from @var{a} with scaling, then add the\n> +result to the accumulator @var{acc}, performing all operations modulo 2^128.\n> +\n> +@subsubheading Merge Operations\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsmerge2t1uqm (vector unsigned __int128 @var{a},\n> +                             vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsmerge2t1uqm\n> +\n> +Perform a type 1 merge operation on two unsigned quadword values @var{a}\n> +and @var{b}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsmerge2t2uqm (vector unsigned __int128 @var{a},\n> +                             vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsmerge2t2uqm\n> +\n> +Perform a type 2 merge operation on two unsigned quadword values @var{a}\n> +and @var{b}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsmerge2t3uqm (vector unsigned __int128 @var{a},\n> +                             vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsmerge2t3uqm\n> +\n> +Perform a type 3 merge operation on two unsigned quadword values @var{a}\n> +and @var{b}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsmerge3t1uqm (vector unsigned __int128 @var{acc},\n> +                             vector unsigned __int128 @var{a},\n> +                             vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsmerge3t1uqm\n> +\n> +Perform a type 1 merge operation on two unsigned quadword values @var{a}\n> +and @var{b} with accumulator @var{acc}.\n> +\n> +@subsubheading Rebase Operations\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsrebase2t1uqm (vector unsigned __int128 @var{a},\n> +                              vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsrebase2t1uqm\n> +\n> +Perform a type 1 rebase operation on two unsigned quadword values @var{a}\n> +and @var{b}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsrebase2t2uqm (vector unsigned __int128 @var{a},\n> +                              vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsrebase2t2uqm\n> +\n> +Perform a type 2 rebase operation on two unsigned quadword values @var{a}\n> +and @var{b}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsrebase2t3uqm (vector unsigned __int128 @var{a},\n> +                              vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsrebase2t3uqm\n> +\n> +Perform a type 3 rebase operation on two unsigned quadword values @var{a}\n> +and @var{b}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsrebase2t4uqm (vector unsigned __int128 @var{a},\n> +                              vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsrebase2t4uqm\n> +\n> +Perform a type 4 rebase operation on two unsigned quadword values @var{a}\n> +and @var{b}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsrebase3t1uqm (vector unsigned __int128 @var{acc},\n> +                              vector unsigned __int128 @var{a},\n> +                              vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsrebase3t1uqm\n> +\n> +Perform a type 1 rebase operation on two unsigned quadword values @var{a}\n> +and @var{b} with accumulator @var{acc}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsrebase3t2uqm (vector unsigned __int128 @var{acc},\n> +                              vector unsigned __int128 @var{a},\n> +                              vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsrebase3t2uqm\n> +\n> +Perform a type 2 rebase operation on two unsigned quadword values @var{a}\n> +and @var{b} with accumulator @var{acc}.\n> +\n> +@smallexample\n> +vector unsigned __int128\n> +__builtin_vsx_xsrebase3t3uqm (vector unsigned __int128 @var{acc},\n> +                              vector unsigned __int128 @var{a},\n> +                              vector unsigned __int128 @var{b});\n> +@end smallexample\n> +@findex __builtin_vsx_xsrebase3t3uqm\n> +\n> +Perform a type 3 rebase operation on two unsigned quadword values @var{a}\n> +and @var{b} with accumulator @var{acc}.\n> +\n>  @node PowerPC Hardware Transactional Memory Built-in Functions\n>  @subsection PowerPC Hardware Transactional Memory Built-in Functions\n>  GCC provides two interfaces for accessing the Hardware Transactional\n> diff --git a/gcc/testsuite/gcc.target/powerpc/ecc-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/ecc-builtin-1.c\n> new file mode 100644\n> index 00000000000..2275d50ffdf\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.target/powerpc/ecc-builtin-1.c\n> @@ -0,0 +1,198 @@\n> +/* { dg-do compile } */\n> +/* { dg-options \"-mdejagnu-cpu=future -O2\" } */\n> +\n> +/* Test the ECC (Elliptic Curve Cryptography) acceleration builtins for Power future.\n> +   These instructions support P-256 and P-384 elliptic curve operations. */\n> +\n> +#include <altivec.h>\n> +\n> +/* Test xxmulmul - Multiply-Multiply with scaling */\n> +vector unsigned __int128\n> +test_xxmulmul (vector unsigned long long a, vector unsigned long long b)\n> +{\n> +  return __builtin_vsx_xxmulmul (a, b, 3);\n> +}\n> +\n> +/* Test xxmulmulhiadd - Multiply-Multiply with high add and accumulator */\n> +vector unsigned __int128\n> +test_xxmulmulhiadd (vector unsigned __int128 acc,\n> +                    vector unsigned long long a,\n> +                    vector unsigned long long b)\n> +{\n> +  return __builtin_vsx_xxmulmulhiadd (acc, a, b, 1, 0, 1);\n> +}\n> +\n> +/* Test xxmulmulloadd - Multiply-Multiply low add with accumulator */\n> +vector unsigned __int128\n> +test_xxmulmulloadd (vector unsigned __int128 acc,\n> +                    vector unsigned long long a,\n> +                    vector unsigned long long b)\n> +{\n> +  return __builtin_vsx_xxmulmulloadd (acc, a, b, 1, 0);\n> +}\n> +\n> +/* Test xxssumudm - Scaled sum unsigned doubleword modulo */\n> +vector unsigned __int128\n> +test_xxssumudm (vector unsigned long long a, vector unsigned long long b)\n> +{\n> +  return __builtin_vsx_xxssumudm (a, b, 1);\n> +}\n> +\n> +/* Test xxssumudmc - Scaled sum unsigned doubleword modulo carry */\n> +vector unsigned __int128\n> +test_xxssumudmc (vector unsigned long long a, vector unsigned long long b)\n> +{\n> +  return __builtin_vsx_xxssumudmc (a, b, 0);\n> +}\n> +\n> +/* Test xxssumudmcext - Scaled sum unsigned doubleword modulo carry extended */\n> +vector unsigned __int128\n> +test_xxssumudmcext (vector unsigned long long a,\n> +                    vector unsigned long long b,\n> +                    vector unsigned __int128 c)\n> +{\n> +  return __builtin_vsx_xxssumudmcext (a, b, c, 1);\n> +}\n> +\n> +/* Test xsaddadduqm - Add add unsigned quadword modulo */\n> +vector unsigned __int128\n> +test_xsaddadduqm (vector unsigned __int128 acc,\n> +                  vector unsigned __int128 a,\n> +                  vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsaddadduqm (acc, a, b);\n> +}\n> +\n> +/* Test xsaddaddsuqm - Add add scaled unsigned quadword modulo */\n> +vector unsigned __int128\n> +test_xsaddaddsuqm (vector unsigned __int128 acc,\n> +                   vector unsigned __int128 a,\n> +                   vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsaddaddsuqm (acc, a, b);\n> +}\n> +\n> +/* Test xsaddsubuqm - Add subtract unsigned quadword modulo */\n> +vector unsigned __int128\n> +test_xsaddsubuqm (vector unsigned __int128 acc,\n> +                  vector unsigned __int128 a,\n> +                  vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsaddsubuqm (acc, a, b);\n> +}\n> +\n> +/* Test xsaddsubsuqm - Add subtract scaled unsigned quadword modulo */\n> +vector unsigned __int128\n> +test_xsaddsubsuqm (vector unsigned __int128 acc,\n> +                   vector unsigned __int128 a,\n> +                   vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsaddsubsuqm (acc, a, b);\n> +}\n> +\n> +/* Test xsmerge2t1uqm - Merge type 1 (2-operand) */\n> +vector unsigned __int128\n> +test_xsmerge2t1uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsmerge2t1uqm (a, b);\n> +}\n> +\n> +/* Test xsmerge2t2uqm - Merge type 2 (2-operand) */\n> +vector unsigned __int128\n> +test_xsmerge2t2uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsmerge2t2uqm (a, b);\n> +}\n> +\n> +/* Test xsmerge2t3uqm - Merge type 3 (2-operand) */\n> +vector unsigned __int128\n> +test_xsmerge2t3uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsmerge2t3uqm (a, b);\n> +}\n> +\n> +/* Test xsmerge3t1uqm - Merge type 1 (3-operand with accumulator) */\n> +vector unsigned __int128\n> +test_xsmerge3t1uqm (vector unsigned __int128 acc,\n> +                    vector unsigned __int128 a,\n> +                    vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsmerge3t1uqm (acc, a, b);\n> +}\n> +\n> +/* Test xsrebase2t1uqm - Rebase type 1 (2-operand) */\n> +vector unsigned __int128\n> +test_xsrebase2t1uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsrebase2t1uqm (a, b);\n> +}\n> +\n> +/* Test xsrebase2t2uqm - Rebase type 2 (2-operand) */\n> +vector unsigned __int128\n> +test_xsrebase2t2uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsrebase2t2uqm (a, b);\n> +}\n> +\n> +/* Test xsrebase2t3uqm - Rebase type 3 (2-operand) */\n> +vector unsigned __int128\n> +test_xsrebase2t3uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsrebase2t3uqm (a, b);\n> +}\n> +\n> +/* Test xsrebase2t4uqm - Rebase type 4 (2-operand) */\n> +vector unsigned __int128\n> +test_xsrebase2t4uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsrebase2t4uqm (a, b);\n> +}\n> +\n> +/* Test xsrebase3t1uqm - Rebase type 1 (3-operand with accumulator) */\n> +vector unsigned __int128\n> +test_xsrebase3t1uqm (vector unsigned __int128 acc,\n> +                     vector unsigned __int128 a,\n> +                     vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsrebase3t1uqm (acc, a, b);\n> +}\n> +\n> +/* Test xsrebase3t2uqm - Rebase type 2 (3-operand with accumulator) */\n> +vector unsigned __int128\n> +test_xsrebase3t2uqm (vector unsigned __int128 acc,\n> +                     vector unsigned __int128 a,\n> +                     vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsrebase3t2uqm (acc, a, b);\n> +}\n> +\n> +/* Test xsrebase3t3uqm - Rebase type 3 (3-operand with accumulator) */\n> +vector unsigned __int128\n> +test_xsrebase3t3uqm (vector unsigned __int128 acc,\n> +                     vector unsigned __int128 a,\n> +                     vector unsigned __int128 b)\n> +{\n> +  return __builtin_vsx_xsrebase3t3uqm (acc, a, b);\n> +}\n> +\n> +/* { dg-final { scan-assembler-times {\\mxxmulmul\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxxmulmulhiadd\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxxmulmulloadd\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxxssumudm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxxssumudmc\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxxssumudmcext\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsaddadduqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsaddaddsuqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsaddsubuqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsaddsubsuqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsmerge2t1uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsmerge2t2uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsmerge2t3uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsmerge3t1uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsrebase2t1uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsrebase2t2uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsrebase2t3uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsrebase2t4uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsrebase3t1uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsrebase3t2uqm\\M} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\mxsrebase3t3uqm\\M} 1 } } */","headers":{"Return-Path":"<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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