[{"id":3683624,"web_url":"http://patchwork.ozlabs.org/comment/3683624/","msgid":"<55BD951E-19E4-44B8-89AC-9D16EFE0E768@unpredictable.fr>","list_archive_url":null,"date":"2026-04-28T18:05:22","subject":"Re: [PATCH 6/6] target/i386/mshv: use the register page to set\n registers","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"content":"> On 28. Apr 2026, at 15:50, Doru Blânzeanu wrote:\n> \n> Update mshv_store_regs to use the register page when it is mmapped and\n> valid to set registers.\n> Otherwise use the ioctls to set the registers.\n> \n> Signed-off-by: Doru Blânzeanu \nReviewed-by: Mohamed Mediouni \n\n> ---\n> target/i386/mshv/mshv-cpu.c | 45 +++++++++++++++++++++++++++++++++----\n> 1 file changed, 41 insertions(+), 4 deletions(-)\n> \n> diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\n> index 7949493e97..6bb3e6d4a9 100644\n> --- a/target/i386/mshv/mshv-cpu.c\n> +++ b/target/i386/mshv/mshv-cpu.c\n> @@ -294,14 +294,51 @@ static int set_standard_regs(const CPUState *cpu)\n> return 0;\n> }\n> \n> +static void mshv_set_standard_regs_vp_page(CPUState *cpu)\n> +{\n> + X86CPU *x86cpu = X86_CPU(cpu);\n> + CPUX86State *env = &x86cpu->env;\n> +\n> + env->regs_page->rax = env->regs[R_EAX];\n> + env->regs_page->rbx = env->regs[R_EBX];\n> + env->regs_page->rcx = env->regs[R_ECX];\n> + env->regs_page->rdx = env->regs[R_EDX];\n> + env->regs_page->rsi = env->regs[R_ESI];\n> + env->regs_page->rdi = env->regs[R_EDI];\n> + env->regs_page->rsp = env->regs[R_ESP];\n> + env->regs_page->rbp = env->regs[R_EBP];\n> + env->regs_page->r8 = env->regs[R_R8];\n> + env->regs_page->r9 = env->regs[R_R9];\n> + env->regs_page->r10 = env->regs[R_R10];\n> + env->regs_page->r11 = env->regs[R_R11];\n> + env->regs_page->r12 = env->regs[R_R12];\n> + env->regs_page->r13 = env->regs[R_R13];\n> + env->regs_page->r14 = env->regs[R_R14];\n> + env->regs_page->r15 = env->regs[R_R15];\n> + env->regs_page->rip = env->eip;\n> + lflags_to_rflags(env);\n> + env->regs_page->rflags = env->eflags;\n> +\n> + env->regs_page->dirty |= (1u << HV_X64_REGISTER_CLASS_GENERAL)\n> + | (1u << HV_X64_REGISTER_CLASS_IP)\n> + | (1u << HV_X64_REGISTER_CLASS_FLAGS);\n> +}\n> +\n> int mshv_store_regs(CPUState *cpu)\n> {\n> + X86CPU *x86cpu = X86_CPU(cpu);\n> + CPUX86State *env = &x86cpu->env;\n> int ret;\n> \n> - ret = set_standard_regs(cpu);\n> - if (ret < 0) {\n> - error_report(\"Failed to store standard registers\");\n> - return -1;\n> + /* Use register vp page to optimize registers access */\n> + if (env->regs_page && env->regs_page->isvalid != 0) {\n> + mshv_set_standard_regs_vp_page(cpu);\n> + } else {\n> + ret = set_standard_regs(cpu);\n> + if (ret < 0) {\n> + error_report(\"Failed to store standard registers\");\n> + return -1;\n> + }\n> }\n> \n> return 0;\n> -- \n> 2.53.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=XbUG05CE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=outbound.ms.icloud.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3684011,"web_url":"http://patchwork.ozlabs.org/comment/3684011/","msgid":"","list_archive_url":null,"date":"2026-04-29T11:38:21","subject":"Re: [PATCH 6/6] target/i386/mshv: use the register page to set\n registers","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/people/90753/","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"content":"On Tue, Apr 28, 2026 at 04:50:53PM +0300, Doru Blânzeanu wrote:\n> Update mshv_store_regs to use the register page when it is mmapped and\n> valid to set registers.\n> Otherwise use the ioctls to set the registers.\n> \n> Signed-off-by: Doru Blânzeanu \n> ---\n> target/i386/mshv/mshv-cpu.c | 45 +++++++++++++++++++++++++++++++++----\n> 1 file changed, 41 insertions(+), 4 deletions(-)\n> \n> diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\n> index 7949493e97..6bb3e6d4a9 100644\n> --- a/target/i386/mshv/mshv-cpu.c\n> +++ b/target/i386/mshv/mshv-cpu.c\n> @@ -294,14 +294,51 @@ static int set_standard_regs(const CPUState *cpu)\n> return 0;\n> }\n> \n> +static void mshv_set_standard_regs_vp_page(CPUState *cpu)\n> +{\n> + X86CPU *x86cpu = X86_CPU(cpu);\n> + CPUX86State *env = &x86cpu->env;\n> +\n> + env->regs_page->rax = env->regs[R_EAX];\n> + env->regs_page->rbx = env->regs[R_EBX];\n> + env->regs_page->rcx = env->regs[R_ECX];\n> + env->regs_page->rdx = env->regs[R_EDX];\n> + env->regs_page->rsi = env->regs[R_ESI];\n> + env->regs_page->rdi = env->regs[R_EDI];\n> + env->regs_page->rsp = env->regs[R_ESP];\n> + env->regs_page->rbp = env->regs[R_EBP];\n> + env->regs_page->r8 = env->regs[R_R8];\n> + env->regs_page->r9 = env->regs[R_R9];\n> + env->regs_page->r10 = env->regs[R_R10];\n> + env->regs_page->r11 = env->regs[R_R11];\n> + env->regs_page->r12 = env->regs[R_R12];\n> + env->regs_page->r13 = env->regs[R_R13];\n> + env->regs_page->r14 = env->regs[R_R14];\n> + env->regs_page->r15 = env->regs[R_R15];\n> + env->regs_page->rip = env->eip;\n> + lflags_to_rflags(env);\n> + env->regs_page->rflags = env->eflags;\n> +\n> + env->regs_page->dirty |= (1u << HV_X64_REGISTER_CLASS_GENERAL)\n> + | (1u << HV_X64_REGISTER_CLASS_IP)\n> + | (1u << HV_X64_REGISTER_CLASS_FLAGS);\n> +}\n> +\n> int mshv_store_regs(CPUState *cpu)\n> {\n> + X86CPU *x86cpu = X86_CPU(cpu);\n> + CPUX86State *env = &x86cpu->env;\n> int ret;\n> \n> - ret = set_standard_regs(cpu);\n> - if (ret < 0) {\n> - error_report(\"Failed to store standard registers\");\n> - return -1;\n> + /* Use register vp page to optimize registers access */\n> + if (env->regs_page && env->regs_page->isvalid != 0) {\n> + mshv_set_standard_regs_vp_page(cpu);\n> + } else {\n> + ret = set_standard_regs(cpu);\n> + if (ret < 0) {\n> + error_report(\"Failed to store standard registers\");\n> + return -1;\n> + }\n> }\n\nI think for consistency sake it would be better to also write back\nsregs, but this is reworked in the migration patch series anyway, so we\ncan leave it as is here.\n\n> \n> return 0;\n> -- \n> 2.53.0\n\nReviewed-By: Magnus Kulke ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=Z7OAF+PS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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