[{"id":3683114,"web_url":"http://patchwork.ozlabs.org/comment/3683114/","msgid":"","list_archive_url":null,"date":"2026-04-28T05:16:41","subject":"Re: [PATCH v2 3/3] ddr: socfpga: Add ECC DRAM scrubbing support for\n Gen5/Arria10","submitter":{"id":91590,"url":"http://patchwork.ozlabs.org/api/people/91590/","name":"Sune Brian","email":"briansune@gmail.com"},"content":"On Tue, Apr 28, 2026 at 11:32 AM wrote:\n>\n> From: Alif Zakuan Yuslaimi \n>\n> The SDRAM must first be rewritten by zeroes if ECC is used to initialize\n> the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a\n> case.\n>\n> This implementation turns the caches on temporarily, then overwrites the\n> whole RAM with zeroes, flushes the caches and turns them off again.\n> This provides satisfactory performance.\n>\n> Move common code sdram_init_ecc_bits() to new common file sdram_soc32.c.\n> Preparation for Gen5 uses the same memory initialization function as\n> Arria10.\n>\n> New Kconfig is introduced to enable this implementation only on the default\n> Arria10 and CycloneV boards as this will increase the SPL size which\n> will exceed some Gen5 devices' SPL size limit.\n>\n> Signed-off-by: Tien Fong Chee \n> Signed-off-by: Alif Zakuan Yuslaimi \n> ---\n\nFor GEN5 cyclone V:\nCustom board\n512x16 DDR3 die x 3\nECC supported to max Cyclone V allowed\nNo boot issue on soft / hard reset\n\nlog:\nU-Boot SPL 2026.07-rc1-dirty (Apr 28 2026 - 13:09:08 +0800)\nDDRCAL: Scrubbing ECC RAM (2048 MiB).\nDDRCAL: SDRAM-ECC initialized success with 1057 ms\nTrying to boot from MMC1\n\n\nU-Boot 2026.07-rc1-dirty (Apr 28 2026 - 13:09:08 +0800)\n\nTested-by: Brian Sune \n\n> arch/arm/mach-socfpga/Kconfig | 13 ++++-\n\n> arch/arm/mach-socfpga/spl_gen5.c | 17 ++++++\n> drivers/ddr/altera/Makefile | 4 +-\n\n> drivers/ddr/altera/sdram_gen5.c | 41 ++++++++++++--\n> drivers/ddr/altera/sdram_soc32.c | 85 ++++++++++++++++++++++++++++++\n> drivers/ddr/altera/sdram_soc32.h | 15 ++++++","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=EA7WV+/F;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Mon, 27 Apr 2026\n 22:16:53 -0700 (PDT)","MIME-Version":"1.0","References":"<20260428033230.7777-1-alif.zakuan.yuslaimi@altera.com>\n <20260428033230.7777-4-alif.zakuan.yuslaimi@altera.com>","In-Reply-To":"<20260428033230.7777-4-alif.zakuan.yuslaimi@altera.com>","From":"Sune Brian ","Date":"Tue, 28 Apr 2026 13:16:41 +0800","X-Gm-Features":"AVHnY4J0NOsxrtB7Xw-aDXY1Szl9f23DXz-Gvo7DzWpH61DRaKQqnGuVjuOg-jk","Message-ID":"\n ","Subject":"Re: [PATCH v2 3/3] ddr: socfpga: Add ECC DRAM scrubbing support for\n Gen5/Arria10","To":"alif.zakuan.yuslaimi@altera.com","Cc":"u-boot@lists.denx.de, Marek Vasut ,\n Simon Goldschmidt ,\n Tien Fong Chee , Tom Rini ,\n Yao Zi ,\n Patrice Chotard , Peng Fan ,\n Simon Glass ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}}]