[{"id":3682738,"web_url":"http://patchwork.ozlabs.org/comment/3682738/","msgid":"","list_archive_url":null,"date":"2026-04-27T14:17:24","subject":"Re: [PATCH v2 2/2] pinctrl: qcom: add the TLMM driver for the Nord\n platforms","submitter":{"id":84725,"url":"http://patchwork.ozlabs.org/api/people/84725/","name":"Bjorn Andersson","email":"andersson@kernel.org"},"content":"On Mon, Apr 27, 2026 at 04:00:30PM +0200, Bartosz Golaszewski wrote:\n> diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c\n[..]\n> +enum nord_functions {\n> +\tmsm_mux_gpio,\n> +\tmsm_mux_aoss_cti,\n> +\tmsm_mux_atest_char0,\n> +\tmsm_mux_atest_char1,\n> +\tmsm_mux_atest_char2,\n> +\tmsm_mux_atest_char3,\n> +\tmsm_mux_atest_char_start,\n> +\tmsm_mux_atest_usb20,\n> +\tmsm_mux_atest_usb21,\n> +\tmsm_mux_aud_intfc0_clk,\n> +\tmsm_mux_aud_intfc0_data0,\n> +\tmsm_mux_aud_intfc0_data1,\n> +\tmsm_mux_aud_intfc0_data2,\n> +\tmsm_mux_aud_intfc0_data3,\n> +\tmsm_mux_aud_intfc0_data4,\n> +\tmsm_mux_aud_intfc0_data5,\n> +\tmsm_mux_aud_intfc0_data6,\n> +\tmsm_mux_aud_intfc0_data7,\n> +\tmsm_mux_aud_intfc0_ws,\n> +\tmsm_mux_aud_intfc10_clk,\n> +\tmsm_mux_aud_intfc10_data0,\n> +\tmsm_mux_aud_intfc10_data1,\n> +\tmsm_mux_aud_intfc10_ws,\n> +\tmsm_mux_aud_intfc1_clk,\n> +\tmsm_mux_aud_intfc1_data0,\n> +\tmsm_mux_aud_intfc1_data1,\n> +\tmsm_mux_aud_intfc1_data2,\n> +\tmsm_mux_aud_intfc1_data3,\n> +\tmsm_mux_aud_intfc1_data4,\n> +\tmsm_mux_aud_intfc1_data5,\n> +\tmsm_mux_aud_intfc1_data6,\n> +\tmsm_mux_aud_intfc1_data7,\n\nIs there any reason to keep these 8 \"data\" lanes as separate pingroups?\n\n> +\tmsm_mux_aud_intfc1_ws,\n> +\tmsm_mux_aud_intfc2_clk,\n> +\tmsm_mux_aud_intfc2_data0,\n> +\tmsm_mux_aud_intfc2_data1,\n> +\tmsm_mux_aud_intfc2_data2,\n> +\tmsm_mux_aud_intfc2_data3,\n> +\tmsm_mux_aud_intfc2_ws,\n> +\tmsm_mux_aud_intfc3_clk,\n> +\tmsm_mux_aud_intfc3_data0,\n> +\tmsm_mux_aud_intfc3_data1,\n> +\tmsm_mux_aud_intfc3_ws,\n> +\tmsm_mux_aud_intfc4_clk,\n> +\tmsm_mux_aud_intfc4_data0,\n> +\tmsm_mux_aud_intfc4_data1,\n> +\tmsm_mux_aud_intfc4_ws,\n> +\tmsm_mux_aud_intfc5_clk,\n> +\tmsm_mux_aud_intfc5_data0,\n> +\tmsm_mux_aud_intfc5_data1,\n> +\tmsm_mux_aud_intfc5_ws,\n> +\tmsm_mux_aud_intfc6_clk,\n> +\tmsm_mux_aud_intfc6_data0,\n> +\tmsm_mux_aud_intfc6_data1,\n> +\tmsm_mux_aud_intfc6_ws,\n> +\tmsm_mux_aud_intfc7_clk,\n> +\tmsm_mux_aud_intfc7_data0,\n> +\tmsm_mux_aud_intfc7_data1,\n> +\tmsm_mux_aud_intfc7_ws,\n> +\tmsm_mux_aud_intfc8_clk,\n> +\tmsm_mux_aud_intfc8_data0,\n> +\tmsm_mux_aud_intfc8_data1,\n> +\tmsm_mux_aud_intfc8_ws,\n> +\tmsm_mux_aud_intfc9_clk,\n> +\tmsm_mux_aud_intfc9_data0,\n> +\tmsm_mux_aud_intfc9_ws,\n> +\tmsm_mux_aud_mclk0_mira,\n> +\tmsm_mux_aud_mclk0_mirb,\n> +\tmsm_mux_aud_mclk1_mira,\n> +\tmsm_mux_aud_mclk1_mirb,\n> +\tmsm_mux_aud_mclk2_mira,\n> +\tmsm_mux_aud_mclk2_mirb,\n> +\tmsm_mux_aud_refclk0,\n> +\tmsm_mux_aud_refclk1,\n> +\tmsm_mux_bist_done,\n> +\tmsm_mux_ccu_async_in0,\n> +\tmsm_mux_ccu_async_in1,\n> +\tmsm_mux_ccu_async_in2,\n> +\tmsm_mux_ccu_async_in3,\n> +\tmsm_mux_ccu_async_in4,\n> +\tmsm_mux_ccu_async_in5,\n> +\tmsm_mux_ccu_i2c_scl0,\n\nIf you combine scl and sda, you don't force the DT author to split the\nstate.\n\n> +\tmsm_mux_ccu_i2c_scl1,\n> +\tmsm_mux_ccu_i2c_scl2,\n> +\tmsm_mux_ccu_i2c_scl3,\n> +\tmsm_mux_ccu_i2c_scl4,\n> +\tmsm_mux_ccu_i2c_scl5,\n> +\tmsm_mux_ccu_i2c_scl6,\n> +\tmsm_mux_ccu_i2c_scl7,\n> +\tmsm_mux_ccu_i2c_scl8,\n> +\tmsm_mux_ccu_i2c_scl9,\n> +\tmsm_mux_ccu_i2c_sda0,\n> +\tmsm_mux_ccu_i2c_sda1,\n> +\tmsm_mux_ccu_i2c_sda2,\n> +\tmsm_mux_ccu_i2c_sda3,\n> +\tmsm_mux_ccu_i2c_sda4,\n> +\tmsm_mux_ccu_i2c_sda5,\n> +\tmsm_mux_ccu_i2c_sda6,\n> +\tmsm_mux_ccu_i2c_sda7,\n> +\tmsm_mux_ccu_i2c_sda8,\n> +\tmsm_mux_ccu_i2c_sda9,\n> +\tmsm_mux_ccu_timer0,\n> +\tmsm_mux_ccu_timer1,\n> +\tmsm_mux_ccu_timer10,\n> +\tmsm_mux_ccu_timer11,\n> +\tmsm_mux_ccu_timer12,\n> +\tmsm_mux_ccu_timer13,\n> +\tmsm_mux_ccu_timer14,\n> +\tmsm_mux_ccu_timer15,\n> +\tmsm_mux_ccu_timer2,\n> +\tmsm_mux_ccu_timer3,\n> +\tmsm_mux_ccu_timer4,\n> +\tmsm_mux_ccu_timer5,\n> +\tmsm_mux_ccu_timer6,\n> +\tmsm_mux_ccu_timer7,\n> +\tmsm_mux_ccu_timer8,\n> +\tmsm_mux_ccu_timer9,\n> +\tmsm_mux_clink_debug,\n> +\tmsm_mux_dbg_out,\n> +\tmsm_mux_dbg_out_clk,\n> +\tmsm_mux_ddr_bist_complete,\n> +\tmsm_mux_ddr_bist_fail,\n> +\tmsm_mux_ddr_bist_start,\n> +\tmsm_mux_ddr_bist_stop,\n> +\tmsm_mux_ddr_pxi0,\n> +\tmsm_mux_ddr_pxi1,\n> +\tmsm_mux_ddr_pxi10,\n> +\tmsm_mux_ddr_pxi11,\n> +\tmsm_mux_ddr_pxi12,\n> +\tmsm_mux_ddr_pxi13,\n> +\tmsm_mux_ddr_pxi14,\n> +\tmsm_mux_ddr_pxi15,\n> +\tmsm_mux_ddr_pxi2,\n> +\tmsm_mux_ddr_pxi3,\n> +\tmsm_mux_ddr_pxi4,\n> +\tmsm_mux_ddr_pxi5,\n> +\tmsm_mux_ddr_pxi6,\n> +\tmsm_mux_ddr_pxi7,\n> +\tmsm_mux_ddr_pxi8,\n> +\tmsm_mux_ddr_pxi9,\n\nThese can be a single group. Perhaps all the ddr_* is a single group?\n\n> +\tmsm_mux_dp_rx0,\n> +\tmsm_mux_dp_rx00,\n> +\tmsm_mux_dp_rx01,\n> +\tmsm_mux_dp_rx0_mute,\n> +\tmsm_mux_dp_rx1,\n> +\tmsm_mux_dp_rx10,\n> +\tmsm_mux_dp_rx11,\n> +\tmsm_mux_dp_rx1_mute,\n> +\tmsm_mux_edp0_hot,\n> +\tmsm_mux_edp0_lcd,\n> +\tmsm_mux_edp1_hot,\n> +\tmsm_mux_edp1_lcd,\n> +\tmsm_mux_edp2_hot,\n> +\tmsm_mux_edp2_lcd,\n> +\tmsm_mux_edp3_hot,\n> +\tmsm_mux_edp3_lcd,\n> +\tmsm_mux_emac0_mcg0,\n> +\tmsm_mux_emac0_mcg1,\n> +\tmsm_mux_emac0_mcg2,\n> +\tmsm_mux_emac0_mcg3,\n\nSingle group?\n\n> +\tmsm_mux_emac0_mdc,\n> +\tmsm_mux_emac0_mdio,\n> +\tmsm_mux_emac0_ptp,\n> +\tmsm_mux_emac1_mcg0,\n> +\tmsm_mux_emac1_mcg1,\n> +\tmsm_mux_emac1_mcg2,\n> +\tmsm_mux_emac1_mcg3,\n> +\tmsm_mux_emac1_mdc,\n> +\tmsm_mux_emac1_mdio,\n> +\tmsm_mux_emac1_ptp,\n> +\tmsm_mux_gcc_gp1_clk,\n> +\tmsm_mux_gcc_gp2_clk,\n> +\tmsm_mux_gcc_gp3_clk,\n> +\tmsm_mux_gcc_gp4_clk,\n> +\tmsm_mux_gcc_gp5_clk,\n> +\tmsm_mux_gcc_gp6_clk,\n> +\tmsm_mux_gcc_gp7_clk,\n> +\tmsm_mux_gcc_gp8_clk,\n> +\tmsm_mux_jitter_bist,\n> +\tmsm_mux_lbist_pass,\n> +\tmsm_mux_mbist_pass,\n> +\tmsm_mux_mdp0_vsync0_out,\n> +\tmsm_mux_mdp0_vsync10_out,\n> +\tmsm_mux_mdp0_vsync1_out,\n> +\tmsm_mux_mdp0_vsync2_out,\n> +\tmsm_mux_mdp0_vsync3_out,\n> +\tmsm_mux_mdp0_vsync4_out,\n> +\tmsm_mux_mdp0_vsync5_out,\n> +\tmsm_mux_mdp0_vsync6_out,\n> +\tmsm_mux_mdp0_vsync7_out,\n> +\tmsm_mux_mdp0_vsync8_out,\n> +\tmsm_mux_mdp0_vsync9_out,\n> +\tmsm_mux_mdp1_vsync0_out,\n> +\tmsm_mux_mdp1_vsync10_out,\n> +\tmsm_mux_mdp1_vsync1_out,\n> +\tmsm_mux_mdp1_vsync2_out,\n> +\tmsm_mux_mdp1_vsync3_out,\n> +\tmsm_mux_mdp1_vsync4_out,\n> +\tmsm_mux_mdp1_vsync5_out,\n> +\tmsm_mux_mdp1_vsync6_out,\n> +\tmsm_mux_mdp1_vsync7_out,\n> +\tmsm_mux_mdp1_vsync8_out,\n> +\tmsm_mux_mdp1_vsync9_out,\n> +\tmsm_mux_mdp_vsync_e,\n> +\tmsm_mux_mdp_vsync_p,\n> +\tmsm_mux_mdp_vsync_s,\n> +\tmsm_mux_pcie0_clk_req_n,\n> +\tmsm_mux_pcie1_clk_req_n,\n> +\tmsm_mux_pcie2_clk_req_n,\n> +\tmsm_mux_pcie3_clk_req_n,\n> +\tmsm_mux_phase_flag0,\n> +\tmsm_mux_phase_flag1,\n> +\tmsm_mux_phase_flag10,\n> +\tmsm_mux_phase_flag11,\n> +\tmsm_mux_phase_flag12,\n> +\tmsm_mux_phase_flag13,\n> +\tmsm_mux_phase_flag14,\n> +\tmsm_mux_phase_flag15,\n> +\tmsm_mux_phase_flag16,\n> +\tmsm_mux_phase_flag17,\n> +\tmsm_mux_phase_flag18,\n> +\tmsm_mux_phase_flag19,\n> +\tmsm_mux_phase_flag2,\n> +\tmsm_mux_phase_flag20,\n> +\tmsm_mux_phase_flag21,\n> +\tmsm_mux_phase_flag22,\n> +\tmsm_mux_phase_flag23,\n> +\tmsm_mux_phase_flag24,\n> +\tmsm_mux_phase_flag25,\n> +\tmsm_mux_phase_flag26,\n> +\tmsm_mux_phase_flag27,\n> +\tmsm_mux_phase_flag28,\n> +\tmsm_mux_phase_flag29,\n> +\tmsm_mux_phase_flag3,\n> +\tmsm_mux_phase_flag30,\n> +\tmsm_mux_phase_flag31,\n> +\tmsm_mux_phase_flag4,\n> +\tmsm_mux_phase_flag5,\n> +\tmsm_mux_phase_flag6,\n> +\tmsm_mux_phase_flag7,\n> +\tmsm_mux_phase_flag8,\n> +\tmsm_mux_phase_flag9,\n\nSingle group.\n\n> +\tmsm_mux_pll_bist_sync,\n> +\tmsm_mux_pll_clk_aux,\n> +\tmsm_mux_prng_rosc0,\n> +\tmsm_mux_prng_rosc1,\n> +\tmsm_mux_pwrbrk_i_n,\n> +\tmsm_mux_qdss_cti,\n> +\tmsm_mux_qdss_gpio,\n> +\tmsm_mux_qdss_gpio0,\n> +\tmsm_mux_qdss_gpio1,\n> +\tmsm_mux_qdss_gpio10,\n> +\tmsm_mux_qdss_gpio11,\n> +\tmsm_mux_qdss_gpio12,\n> +\tmsm_mux_qdss_gpio13,\n> +\tmsm_mux_qdss_gpio14,\n> +\tmsm_mux_qdss_gpio15,\n> +\tmsm_mux_qdss_gpio2,\n> +\tmsm_mux_qdss_gpio3,\n> +\tmsm_mux_qdss_gpio4,\n> +\tmsm_mux_qdss_gpio5,\n> +\tmsm_mux_qdss_gpio6,\n> +\tmsm_mux_qdss_gpio7,\n> +\tmsm_mux_qdss_gpio8,\n> +\tmsm_mux_qdss_gpio9,\n\nSingle group. Perhaps even single \"qdss\" group?\n\n> +\tmsm_mux_qspi0,\n> +\tmsm_mux_qspi1,\n> +\tmsm_mux_qspi2,\n> +\tmsm_mux_qspi3,\n\nSingle group.\n\n> +\tmsm_mux_qspi_clk,\n> +\tmsm_mux_qspi_cs0_n,\n> +\tmsm_mux_qspi_cs1_n,\n> +\tmsm_mux_qup0_se0,\n> +\tmsm_mux_qup0_se1,\n> +\tmsm_mux_qup0_se2,\n> +\tmsm_mux_qup0_se3,\n> +\tmsm_mux_qup0_se4,\n> +\tmsm_mux_qup0_se5,\n> +\tmsm_mux_qup1_se0,\n> +\tmsm_mux_qup1_se1,\n> +\tmsm_mux_qup1_se2,\n> +\tmsm_mux_qup1_se3,\n> +\tmsm_mux_qup1_se4,\n> +\tmsm_mux_qup1_se5,\n> +\tmsm_mux_qup1_se6,\n> +\tmsm_mux_qup2_se0,\n> +\tmsm_mux_qup2_se1,\n> +\tmsm_mux_qup2_se2,\n> +\tmsm_mux_qup2_se3,\n> +\tmsm_mux_qup2_se4,\n> +\tmsm_mux_qup2_se5,\n> +\tmsm_mux_qup2_se6,\n> +\tmsm_mux_qup3_se0_mira,\n> +\tmsm_mux_qup3_se0_mirb,\n\nNice, that's clean.\n\nRegards,\nBjorn","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=OaDTs7Ak;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260427-nord-tlmm-v2-2-ade8e0f3d803@oss.qualcomm.com>"}},{"id":3682744,"web_url":"http://patchwork.ozlabs.org/comment/3682744/","msgid":"","list_archive_url":null,"date":"2026-04-27T14:19:16","subject":"Re: [PATCH v2 2/2] pinctrl: qcom: add the TLMM driver for the Nord\n platforms","submitter":{"id":92191,"url":"http://patchwork.ozlabs.org/api/people/92191/","name":"Bartosz Golaszewski","email":"brgl@kernel.org"},"content":"On Mon, Apr 27, 2026 at 4:17 PM Bjorn Andersson wrote:\n>\n> On Mon, Apr 27, 2026 at 04:00:30PM +0200, Bartosz Golaszewski wrote:\n> > diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c\n> [..]\n> > +enum nord_functions {\n> > + msm_mux_gpio,\n> > + msm_mux_aoss_cti,\n> > + msm_mux_atest_char0,\n> > + msm_mux_atest_char1,\n> > + msm_mux_atest_char2,\n> > + msm_mux_atest_char3,\n> > + msm_mux_atest_char_start,\n> > + msm_mux_atest_usb20,\n> > + msm_mux_atest_usb21,\n> > + msm_mux_aud_intfc0_clk,\n> > + msm_mux_aud_intfc0_data0,\n> > + msm_mux_aud_intfc0_data1,\n> > + msm_mux_aud_intfc0_data2,\n> > + msm_mux_aud_intfc0_data3,\n> > + msm_mux_aud_intfc0_data4,\n> > + msm_mux_aud_intfc0_data5,\n> > + msm_mux_aud_intfc0_data6,\n> > + msm_mux_aud_intfc0_data7,\n> > + msm_mux_aud_intfc0_ws,\n> > + msm_mux_aud_intfc10_clk,\n> > + msm_mux_aud_intfc10_data0,\n> > + msm_mux_aud_intfc10_data1,\n> > + msm_mux_aud_intfc10_ws,\n> > + msm_mux_aud_intfc1_clk,\n> > + msm_mux_aud_intfc1_data0,\n> > + msm_mux_aud_intfc1_data1,\n> > + msm_mux_aud_intfc1_data2,\n> > + msm_mux_aud_intfc1_data3,\n> > + msm_mux_aud_intfc1_data4,\n> > + msm_mux_aud_intfc1_data5,\n> > + msm_mux_aud_intfc1_data6,\n> > + msm_mux_aud_intfc1_data7,\n>\n> Is there any reason to keep these 8 \"data\" lanes as separate pingroups?\n>\n\nThe answer here and elsewhere is: no. I just didn't have other states\nin DTS to visualize the resulting nodes and it didn't occur to me to\nupdate other functions as well. I'll do it in v3.\n\nBart","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=ecOilbna;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35587-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"ecOilbna\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g45Qf1nHgz1xvV\n\tfor ; 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Mon, 27 Apr 2026\n 07:19:29 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20260427-nord-tlmm-v2-0-ade8e0f3d803@oss.qualcomm.com>\n <20260427-nord-tlmm-v2-2-ade8e0f3d803@oss.qualcomm.com>\n ","In-Reply-To":"","From":"Bartosz Golaszewski ","Date":"Mon, 27 Apr 2026 16:19:16 +0200","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AVHnY4KLKvQTIww_LmXI9MwhW94zXNui82mwS-N0sdDW_fPy6iQj1PtiDTKMtIA","Message-ID":"\n ","Subject":"Re: [PATCH v2 2/2] pinctrl: qcom: add the TLMM driver for the Nord\n platforms","To":"Bjorn Andersson ","Cc":"Bartosz Golaszewski ,\n Linus Walleij ,\n\tRob Herring , Krzysztof Kozlowski ,\n Conor Dooley ,\n\tRichard Cochran ,\n Shawn Guo ,\n\tArnd Bergmann ,\n Dmitry Baryshkov ,\n\tlinux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tnetdev@vger.kernel.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3682755,"web_url":"http://patchwork.ozlabs.org/comment/3682755/","msgid":"","list_archive_url":null,"date":"2026-04-27T14:33:21","subject":"Re: [PATCH v2 2/2] pinctrl: qcom: add the TLMM driver for the Nord\n platforms","submitter":{"id":89450,"url":"http://patchwork.ozlabs.org/api/people/89450/","name":"Konrad Dybcio","email":"konrad.dybcio@oss.qualcomm.com"},"content":"On 4/27/26 4:00 PM, Bartosz Golaszewski wrote:\n> Add support for the TLMM controller on the Qualcomm Nord platform.\n> \n> Co-developed-by: Shawn Guo \n> Signed-off-by: Shawn Guo \n> Reviewed-by: Dmitry Baryshkov \n> Signed-off-by: Bartosz Golaszewski \n> ---\n\n[...]\n\n> +\t[177] = PINGROUP(177, ccu_async_in1, atest_char0, _, _, _, _, _, _, _, _, _),\n> +\t[178] = PINGROUP(178, ccu_async_in2, atest_char1, _, _, _, _, _, _, _, _, _),\n> +\t[179] = PINGROUP(179, ccu_async_in3, atest_char2, _, _, _, _, _, _, _, _, _),\n> +\t[180] = PINGROUP(180, ccu_async_in4, atest_char3, _, _, _, _, _, _, _, _, _),\n> +\t[181] = UFS_RESET(ufs_reset, 0xBD004),\n\nlowercase hex, please\n\nYou'll also need to alter the macro definition - the CTL reg is where\nyou suggest, but the IO reg is at +0xbe000\n\nKonrad","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=UcbvvKZU;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=jchMWZoH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3683423,"web_url":"http://patchwork.ozlabs.org/comment/3683423/","msgid":"<9dd3aa94-0306-47ab-8bc8-ec5ac4219f31@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-28T11:54:55","subject":"Re: [PATCH v2 2/2] pinctrl: qcom: add the TLMM driver for the Nord\n platforms","submitter":{"id":91285,"url":"http://patchwork.ozlabs.org/api/people/91285/","name":"Pankaj Patil","email":"pankaj.patil@oss.qualcomm.com"},"content":"On 4/27/2026 7:30 PM, Bartosz Golaszewski wrote:\n> Add support for the TLMM controller on the Qualcomm Nord platform.\n> \n> Co-developed-by: Shawn Guo \n> Signed-off-by: Shawn Guo \n> Reviewed-by: Dmitry Baryshkov \n> Signed-off-by: Bartosz Golaszewski \n> ---\n> drivers/pinctrl/qcom/Kconfig.msm | 7 +\n> drivers/pinctrl/qcom/Makefile | 1 +\n> drivers/pinctrl/qcom/pinctrl-nord.c | 2843 +++++++++++++++++++++++++++++++++++\n> 3 files changed, 2851 insertions(+)\n> \n> diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm\n> index 836cdeca1006ff7ad5030ac5c537d775d3f0261b..67124ac607baa0f317e0713760a0a2fefba1e2de 100644\n> --- a/drivers/pinctrl/qcom/Kconfig.msm\n> +++ b/drivers/pinctrl/qcom/Kconfig.msm\n> @@ -229,6 +229,13 @@ config PINCTRL_MSM8998\n> \t This is the pinctrl, pinmux, pinconf and gpiolib driver for the\n> \t Qualcomm TLMM block found in the Qualcomm MSM8998 platform.\n> \n> +config PINCTRL_NORD\n> +\ttristate \"Qualcomm Technologies Inc NORD (SA8797p) pin controller driver\"\n> +\tdepends on ARM64 || COMPILE_TEST\n\n+ default ARCH_QCOM\nAccording to Krzysztof's patch,\nhttps://lore.kernel.org/all/20260425155505.83688-2-krzysztof.kozlowski@oss.qualcomm.com/\n\n> +\thelp\n> +\t This is the pinctrl, pinmux and pinconf driver for the Qualcomm\n> +\t TLMM block found on the Qualcomm NORD platforms.\n> +\n> config PINCTRL_QCM2290\n> \ttristate \"Qualcomm QCM2290 pin controller driver\"\n> \tdepends on ARM64 || COMPILE_TEST","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=BHdeZn1Z;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=BHgtB7Vr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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