[{"id":3683076,"web_url":"http://patchwork.ozlabs.org/comment/3683076/","msgid":"","list_archive_url":null,"date":"2026-04-28T02:24:53","subject":"Re: [PATCH v4 20/32] target/riscv: Register target_get_monitor_def in\n SysemuCPUOps","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Mon, Apr 27, 2026 at 6:11 PM Philippe Mathieu-Daudé\n wrote:\n>\n> Rename target_get_monitor_def() as riscv_monitor_get_register_legacy()\n> and register it as SysemuCPUOps::monitor_get_register() handler.\n> Take care to sign-extend values for 32-bit HARTs.\n>\n> Signed-off-by: Philippe Mathieu-Daudé \n> Reviewed-by: Richard Henderson \n\nAcked-by: Alistair Francis \n\nAlistair\n\n> ---\n> target/riscv/internals.h | 3 +++\n> target/riscv/cpu.c | 1 +\n> target/riscv/monitor.c | 11 +++++++----\n> 3 files changed, 11 insertions(+), 4 deletions(-)\n>\n> diff --git a/target/riscv/internals.h b/target/riscv/internals.h\n> index 35b923c4bf5..47becca37f2 100644\n> --- a/target/riscv/internals.h\n> +++ b/target/riscv/internals.h\n> @@ -233,4 +233,7 @@ static inline int insn_len(uint16_t first_word)\n> return (first_word & 3) == 3 ? 4 : 2;\n> }\n>\n> +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,\n> + int64_t *pval);\n> +\n> #endif\n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index 8ac935ac06e..dbd88fa6655 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -2720,6 +2720,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {\n> .get_phys_page_debug = riscv_cpu_get_phys_page_debug,\n> .write_elf64_note = riscv_cpu_write_elf64_note,\n> .write_elf32_note = riscv_cpu_write_elf32_note,\n> + .monitor_get_register = riscv_monitor_get_register_legacy,\n> .legacy_vmsd = &vmstate_riscv_cpu,\n> };\n> #endif\n> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c\n> index bca04a7580c..3898595a3cb 100644\n> --- a/target/riscv/monitor.c\n> +++ b/target/riscv/monitor.c\n> @@ -27,6 +27,7 @@\n> #include \"monitor/hmp.h\"\n> #include \"monitor/hmp-target.h\"\n> #include \"system/memory.h\"\n> +#include \"internals.h\"\n>\n> #ifdef TARGET_RISCV64\n> #define PTE_HEADER_FIELDS \"vaddr paddr \"\\\n> @@ -311,16 +312,18 @@ static bool reg_is_vreg(const char *name)\n> return false;\n> }\n>\n> -int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)\n> +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,\n> + int64_t *pval)\n> {\n> - CPURISCVState *env = &RISCV_CPU(cs)->env;\n> + RISCVCPU *hart = RISCV_CPU(cs);\n> + CPURISCVState *env = cpu_env(cs);\n> target_ulong val = 0;\n> uint64_t val64 = 0;\n> int i;\n>\n> if (reg_is_ulong_integer(env, name, &val, false) ||\n> reg_is_ulong_integer(env, name, &val, true)) {\n> - *pval = val;\n> + *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;\n> return 0;\n> }\n>\n> @@ -369,7 +372,7 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)\n> * to do the filtering of the registers that are present.\n> */\n> if (res == RISCV_EXCP_NONE) {\n> - *pval = val;\n> + *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;\n> return 0;\n> }\n> }\n> --\n> 2.53.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=hqoSN4pv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4PS31FfRz1yHX\n\tfor ; Tue, 28 Apr 2026 12:25:55 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHY8g-0002VX-O6; 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