[{"id":3682216,"web_url":"http://patchwork.ozlabs.org/comment/3682216/","msgid":"<07641306-35d0-4b51-915e-15af1bf09a6b@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-24T21:53:56","subject":"Re: [PATCH] RISC-V: Missed bit manipulation on RISC-V [PR123884]","submitter":{"id":92310,"url":"http://patchwork.ozlabs.org/api/people/92310/","name":"Jeffrey Law","email":"jeffrey.law@oss.qualcomm.com"},"content":"On 4/24/2026 10:27 AM, Milan Tripkovic wrote:\n> This patch implements new patterns for bclr, binv and bset,\n> which fix the problem with bad code generation in\n> PR123884.\n> foo2before:\n>     li a5,1\n>     sllw a5,a5,a1\n>     or a0,a0,a5\n>     Ret\n> Foo2after:\n>     bset a0, a0, a1\n>     sext.w a0, a0\n>     Ret\n> 2026-04-24  Milan Tripkovic \n>\n> gcc/ChangeLog:\n>\n>       * config/riscv/bitmanip.md (_sextw_pair): new pattern for \n> binv and bset\n>       (bclr_sextw_pair): new pattern for bclr\n>\n> gcc/testsuite/ChangeLog:\n>\n>       * gcc.target/riscv/pr123884-a.c: New test for new pattern\n>       * gcc.target/riscv/pr123884-b.c: New test for new pattern\n>       * gcc.target/riscv/pr123884-c.c: New test for new pattern\nI think it does the right thing for IOR when bit 31 is turned on, but \nnot for XOR/AND.\n\nThe key thing to think about is bits 31..63 and where they come from.\n\nIn the IOR case if we're turning on bit 31, then bits 32..63 also get \nturned on irrespective of the value in operands[2].\n\nIn the XOR case if we're turning on bit 31, then bits 32..63 are \ninverted values from operands[2], but the new RTL doesn't have those \nsemantics.  It'll make bits 32..63 copies of bit 31.\n\nFor the AND case if we turn off bit 31, then the result is operands[2] \nwith bit 31 and only bit 31 turned off.  But the new RTL would have bits \n32..63 as copies of bit 31.\n\nSo I think we could take the first pattern and limit it to IOR.  I don't \nthink we have a good solution for XOR/AND and I'm terribly sorry if I \nsent you down a rat hole for the XOR/AND case -- the more I think about \nthat case the more I believe that it's not possible to handle without \nknowing that bits 32.63 are OK as sign bit copies. While I have \nprototyped some code in that space, it's nowhere near ready for real use.\n\nSo I find myself thinking we should simplify this patch to just the IOR \ncase.  It won't fully resolve 123884, but it's a step forward while we \nponder how to improve the XOR/AND cases.\n\njeff\n\n\n\n\n\n>\n>\n>\n>\n> CONFIDENTIALITY: The contents of this e-mail are confidential and \n> intended only for the above addressee(s). If you are not the intended \n> recipient, or the person responsible for delivering it to the intended \n> recipient, copying or delivering it to anyone else or using it in any \n> unauthorized manner is prohibited and may be unlawful. If you receive \n> this e-mail by mistake, please notify the sender and the systems \n> administrator at straymail@rt-rk.com immediately.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=PFFTjOdw;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=etDXkfmK;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n 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","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3682220,"web_url":"http://patchwork.ozlabs.org/comment/3682220/","msgid":"","list_archive_url":null,"date":"2026-04-24T22:11:57","subject":"Re: [PATCH] RISC-V: Missed bit manipulation on RISC-V [PR123884]","submitter":{"id":77655,"url":"http://patchwork.ozlabs.org/api/people/77655/","name":"Andrew Waterman","email":"aswaterman@gmail.com"},"content":"Even in the IOR case, isn't there a problem for shift amounts >= 32?\nThe `slliw` takes the shift amount mod 32, but the `bset` takes it mod\n64. Granted, this case would correspond to undefined behavior in C,\nbut I don't know how that relates to the IR's semantics.\n\n\nOn Fri, Apr 24, 2026 at 2:54 PM Jeffrey Law\n wrote:\n>\n>\n>\n> On 4/24/2026 10:27 AM, Milan Tripkovic wrote:\n>\n> This patch implements new patterns for bclr, binv and bset,\n> which fix the problem with bad code generation in\n> PR123884.\n> foo2before:\n>     li a5,1\n>     sllw a5,a5,a1\n>     or a0,a0,a5\n>     Ret\n> Foo2after:\n>     bset a0, a0, a1\n>     sext.w a0, a0\n>     Ret\n>\n> 2026-04-24 Milan Tripkovic \n>\n> gcc/ChangeLog:\n>\n>       * config/riscv/bitmanip.md (_sextw_pair): new pattern for binv and bset\n>       (bclr_sextw_pair): new pattern for bclr\n>\n> gcc/testsuite/ChangeLog:\n>\n>       * gcc.target/riscv/pr123884-a.c: New test for new pattern\n>       * gcc.target/riscv/pr123884-b.c: New test for new pattern\n>       * gcc.target/riscv/pr123884-c.c: New test for new pattern\n>\n> I think it does the right thing for IOR when bit 31 is turned on, but not for XOR/AND.\n>\n> The key thing to think about is bits 31..63 and where they come from.\n>\n> In the IOR case if we're turning on bit 31, then bits 32..63 also get turned on irrespective of the value in operands[2].\n>\n> In the XOR case if we're turning on bit 31, then bits 32..63 are inverted values from operands[2], but the new RTL doesn't have those semantics. It'll make bits 32..63 copies of bit 31.\n>\n> For the AND case if we turn off bit 31, then the result is operands[2] with bit 31 and only bit 31 turned off. But the new RTL would have bits 32..63 as copies of bit 31.\n>\n> So I think we could take the first pattern and limit it to IOR. I don't think we have a good solution for XOR/AND and I'm terribly sorry if I sent you down a rat hole for the XOR/AND case -- the more I think about that case the more I believe that it's not possible to handle without knowing that bits 32.63 are OK as sign bit copies. While I have prototyped some code in that space, it's nowhere near ready for real use.\n>\n> So I find myself thinking we should simplify this patch to just the IOR case. It won't fully resolve 123884, but it's a step forward while we ponder how to improve the XOR/AND cases.\n>\n> jeff\n>\n>\n>\n>\n>\n>\n>\n>\n>\n> CONFIDENTIALITY: The contents of this e-mail are confidential and intended only for the above addressee(s). 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Granted, this case would correspond to undefined behavior in C,\n> but I don't know how that relates to the IR's semantics.\nCount will never be >= 32 here as the shift operation is done in \nSImode.  If it somehow managed to sneak through it'd be undefined behavior.\n\nBut it's a good thing to be aware of.  We had just this sort of bug \nraise its head a year or two ago.\n\njeff","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Ri3LZCgR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Ri3LZCgR","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","sourceware.org; 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