[{"id":3682140,"web_url":"http://patchwork.ozlabs.org/comment/3682140/","msgid":"<20260424-mumps-foothill-ef122c1029c0@spud>","list_archive_url":null,"date":"2026-04-24T16:56:50","subject":"Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","submitter":{"id":84372,"url":"http://patchwork.ozlabs.org/api/people/84372/","name":"Conor Dooley","email":"conor@kernel.org"},"content":"On Fri, Apr 24, 2026 at 04:13:21AM -0700, Changhuang Liang wrote:\n> Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1) pinctrl\n> controller.\n> \n> Signed-off-by: Changhuang Liang \n\nThere's a lot of binding here, and I think a bunch of them have similar\nquestions to be answered, so I am just going to review this one for now.\n\n> ---\n> .../pinctrl/starfive,jhb100-per1-pinctrl.yaml | 217 ++++++++++++++++++\n> 1 file changed, 217 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml\n> \n> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml\n> new file mode 100644\n> index 000000000000..b2af4df874df\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml\n> @@ -0,0 +1,217 @@\n> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n> +%YAML 1.2\n> +---\n> +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.yaml#\n> +$schema: http://devicetree.org/meta-schemas/core.yaml#\n> +\n> +title: StarFive JHB100 Peripheral-1 Pin Controller\n> +\n> +description: |\n> + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.\n> +\n> + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,\n> + per2, per2pok, per3, adc0, adc1, emmc, and vga.\n> + This document provides an overview of the \"per1\" pinctrl domain.\n> +\n> + The \"per1\" domain has a pin controller which provides\n> + - function selection for GPIO pads.\n> + - GPIO pad configuration.\n> + - GPIO interrupt handling.\n> +\n> + In the Peripheral-1 Pin Controller, there are 36 multi-function GPIO_PADs. Each of them\n> + can be multiplexed to several peripherals through function selection. Each iopad has a\n> + maximum of up to 3 functions - 0, 1, and 2. Function 0 is the default function which is\n> + generally the GPIO function. Function 1 and 2 are the alternate functions or peripheral\n> + signals that can be routed to the iopad. The function selection can be carried out by\n> + writing the function number to the iopad function select register.\n> + Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down\n> + bias, drive strength, schmitt trigger, slew rate, and debounce width.\n> +\n> + This domain contains 4 IO groups which support voltage levels 1.8V and 3.3V\n> + gpioe-spi - comprises PAD_GPIO_C0 through PAD_GPIO_C4.\n> + gpioe-qspi0 - comprises PAD_GPIO_C5 through PAD_GPIO_C11.\n> + gpioe-qspi1 - comprises PAD_GPIO_C12 through PAD_GPIO_C19.\n> + gpioe-qspi2 - comprises PAD_GPIO_C20 through PAD_GPIO_C27.\n> +\n> + Each of the above IO groups must be configured with a voltage setting that matches the external\n> + voltage level provided to the IO group.\n> +\n> +maintainers:\n> + - Alex Soo \n> +\n> +properties:\n> + compatible:\n> + items:\n> + - const: starfive,jhb100-per1-pinctrl\n> +\n> + reg:\n> + maxItems: 1\n> +\n> + clocks:\n> + maxItems: 1\n> +\n> + resets:\n> + maxItems: 1\n> +\n> + interrupts:\n> + maxItems: 1\n> +\n> + interrupt-controller: true\n> +\n> + '#interrupt-cells':\n> + const: 2\n> +\n> + gpio-controller: true\n> +\n> + '#gpio-cells':\n> + const: 2\n> +\n> + gpio-ranges:\n> + maxItems: 1\n> +\n> + gpio-line-names: true\n> +\n> + gpioe-spi-vref:\n\nWhy are these custom properties required?\nThis sounds like the sort of information that could be gleaned from the\n\"power-source\" property.\n\n> + description: |\n> + Voltage reference value for the IO group \"gpioe-spi\"\n> + 0: voltage reference value for 3.3V\n> + 2: voltage reference value for 1.8V\n> + $ref: /schemas/types.yaml#/definitions/uint32\n> + enum: [0, 2]\n> + default: 0\n> +\n> + gpioe-qspi0-vref:\n> + description: |\n> + Voltage reference value for the IO group \"gpioe-qspi0\"\n> + 0: voltage reference value for 3.3V\n> + 2: voltage reference value for 1.8V\n> + $ref: /schemas/types.yaml#/definitions/uint32\n> + enum: [0, 2]\n> + default: 0\n> +\n> + gpioe-qspi1-vref:\n> + description: |\n> + Voltage reference value for the IO group \"gpioe-qspi1\"\n> + 0: voltage reference value for 3.3V\n> + 2: voltage reference value for 1.8V\n> + $ref: /schemas/types.yaml#/definitions/uint32\n> + enum: [0, 2]\n> + default: 0\n> +\n> + gpioe-qspi2-vref:\n> + description: |\n> + Voltage reference value for the IO group \"gpioe-qspi2\"\n> + 0: voltage reference value for 3.3V\n> + 2: voltage reference value for 1.8V\n> + $ref: /schemas/types.yaml#/definitions/uint32\n> + enum: [0, 2]\n> + default: 0\n> +\n> +patternProperties:\n> + '-grp$':\n> + type: object\n> + additionalProperties: false\n> + patternProperties:\n> + '-pins$':\n> + type: object\n> + description: |\n> + A pinctrl node should contain at least one subnode representing the\n> + pinctrl groups available in the domain. Each subnode will list the\n> + pins it needs, and how they should be configured, with regard to\n> + function selection, bias, input enable/disable, input schmitt\n> + trigger enable/disable, slew-rate and drive strength.\n> + allOf:\n> + - $ref: /schemas/pinctrl/pincfg-node.yaml\n> + - $ref: /schemas/pinctrl/pinmux-node.yaml\n> + unevaluatedProperties: false\n> +\n> + properties:\n> + pinmux:\n> + description: |\n> + The list of GPIOs and their function select.\n> + The PINMUX macros are used to configure the\n> + function selection.\n\nWhy is the pinmux property needed?\nCan you use pins and function instead?\n\nLooking at the defines that you have added, it appears that lots of\ndefines for the same peripheral share the same numerical values,\nsuggesting that across peripheral, all (or most) pins would share the\nsame mux setting/\"function select\", suggesting that pins/function would\nsuffice.\n\nI'd like to see some justification for pinmux being the right solution\nhere, like the \"function select\" used by one peripheral being\nsignificantly different for many of its pins.\n\n> +\n> + bias-disable: true\n> +\n> + bias-pull-up:\n> + type: boolean\n> +\n> + bias-pull-down:\n> + type: boolean\n> +\n> + drive-strength:\n> + enum: [ 2, 4, 8, 12 ]\n> +\n> + drive-strength-microamp:\n> + enum: [ 2000, 4000, 8000, 12000 ]\n> +\n> + input-enable: true\n> +\n> + input-disable: true\n> +\n> + input-schmitt-enable: true\n> +\n> + input-schmitt-disable: true\n> +\n> + slew-rate:\n> + enum: [ 0, 1 ]\n> + default: 0\n> + description: |\n> + 0: slow (half frequency)\n> + 1: fast\n> +\n> + starfive,debounce-width:\n> + $ref: /schemas/types.yaml#/definitions/uint32\n> + default: 0\n> + description:\n> + Debounce width 0 = Disabled, Others = 80ns*N stages\n\nThis sounds like it should be called \"debounce-stages\".\n\n> +\n> + starfive,drive-i2c-fast-mode:\n> + type: boolean\n> + description:\n> + Enable I2C fast mode drive\n> +\n> + starfive,drive-i2c-fast-mode-plus:\n> + type: boolean\n> + description:\n> + Enable I2C fast mode plus drive\n> +\n> + starfive,i2c-open-drain-pull-up-ohm:\n> + $ref: /schemas/types.yaml#/definitions/uint32\n\nThe unit of resistance is \"ohms\" in dt-schema, if you swap to that you\nwon't need the $ref.\n\n> + description:\n> + open drain pull-up select\n> + enum: [600, 900, 1200, 2000]\n> + default: 600\n> +\n> +required:\n> + - compatible\n> + - reg\n> + - resets\n> + - interrupts\n> + - interrupt-controller\n> + - '#interrupt-cells'\n> + - gpio-controller\n> + - '#gpio-cells'\n> + - gpio-ranges\n> +\n> +additionalProperties: false\n> +\n> +examples:\n> + - |\n> + soc {\n> + #address-cells = <2>;\n> + #size-cells = <2>;\n> +\n> + pinctrl_per1: pinctrl@11b42000 {\n\nDrop the label here, since there's no users.\n\n\nCheers,\nConor.\n\n> + compatible = \"starfive,jhb100-per1-pinctrl\";\n> + reg = <0x0 0x11b42000 0x0 0x800>;\n> + resets = <&per1crg 0>;\n> + interrupts = <61>;\n> + interrupt-controller;\n> + #interrupt-cells = <2>;\n> + gpio-controller;\n> + #gpio-cells = <2>;\n> + gpio-ranges = <&pinctrl_per1 0 0 36>;\n> + };\n> + };\n> -- \n> 2.25.1\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=RCdyJj9f;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777049816; cv=none;\n b=XepuVl7l6ENzyNLzasnSiLZ5foBAfyecykN81XcFGpCQvIJ8j3Xmt1ta0iVRPjmk46SJDfbS7Xi5N3awL3p53x2yMg2/WaBcjMYYA5nADo+aeVkeTybgjoFUcjnVJGMf9kapWBWlQj5ZfSP9/BkLqv4GwEyEDXvDpiGAc8Nc7M0=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777049816; c=relaxed/simple;\n\tbh=RfjkBzwZ9edtsWXWfoG26jk4sifBG9YcFnA7yXOM/ww=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=CQQjzgmnCeG0vbM/rBZ8iaGIjGv0FmyXXJUekshZ27OTYufaQG7Xmj3Gr872qf0dQ6RlP08yRdDjYvI6yGQz5dv9luFyHuXeyLFUc0MYItU6gb30gQJ0DUHntSYg47tCtKNuFIJ7AX022hrXnIrl17ZjtbzVKhLV/nzKcfkNchA=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=RCdyJj9f; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777049815;\n\tbh=RfjkBzwZ9edtsWXWfoG26jk4sifBG9YcFnA7yXOM/ww=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=RCdyJj9fNhnq2y2tvCxJyCFSzCyDtzas7v3XsVw++ruxt59N9WECEEAmQxwVhP4uh\n\t OBpEWAyeCzwwuJ5f+MZ6Cp0xes6xhmJTePpo7rqgdqdqL+Ox+B5rmXz3MoLwyvK12Q\n\t 08XlSp1EF427rp3ToZOEI7Bi1cel6CzoP4cCRvqYq8i5S/bowjtWZwBZQTxM+hRj9a\n\t kTZN1M6AkDx5Wtdj6MoOVV3+eBAYAKXXshLiFaTBkeVrUpbH01+FJSHNo9cwGMu/Se\n\t yM3dEGJCtLZQH+sDsbKDf30MI5yrEAturDsSbeLBSWZc/JCaDvBheAk/AzSdSEaT85\n\t L+WS20iHUr2Yw==","Date":"Fri, 24 Apr 2026 17:56:50 +0100","From":"Conor Dooley ","To":"Changhuang Liang ","Cc":"Linus Walleij , Rob Herring ,\n\tKrzysztof Kozlowski ,\n\tConor Dooley ,\n\tEmil Renner Berthing ,\n\tPaul Walmsley , Albert Ou ,\n\tPalmer Dabbelt ,\n\tAlexandre Ghiti ,\n\tPhilipp Zabel ,\n\tBartosz Golaszewski , linux-gpio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-riscv@lists.infradead.org,\n\tLianfeng Ouyang ","Subject":"Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","Message-ID":"<20260424-mumps-foothill-ef122c1029c0@spud>","References":"<20260424111330.702272-1-changhuang.liang@starfivetech.com>\n <20260424111330.702272-12-changhuang.liang@starfivetech.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"+tz+siA7KtiLNcy0\"","Content-Disposition":"inline","In-Reply-To":"<20260424111330.702272-12-changhuang.liang@starfivetech.com>"}},{"id":3683060,"web_url":"http://patchwork.ozlabs.org/comment/3683060/","msgid":"","list_archive_url":null,"date":"2026-04-28T01:28:05","subject":"Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","submitter":{"id":85771,"url":"http://patchwork.ozlabs.org/api/people/85771/","name":"Changhuang Liang","email":"changhuang.liang@starfivetech.com"},"content":"Hi, Conor\n\nThanks for the review.\n\n> On Fri, Apr 24, 2026 at 04:13:21AM -0700, Changhuang Liang wrote:\n> > Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1)\n> > pinctrl controller.\n> >\n> > Signed-off-by: Changhuang Liang \n> \n> There's a lot of binding here, and I think a bunch of them have similar\n> questions to be answered, so I am just going to review this one for now.\n> \n> > ---\n> > .../pinctrl/starfive,jhb100-per1-pinctrl.yaml | 217\n> > ++++++++++++++++++\n> > 1 file changed, 217 insertions(+)\n> > create mode 100644\n> > Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl\n> > .yaml\n> >\n> > diff --git\n> > a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinct\n> > rl.yaml\n> > b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinct\n> > rl.yaml\n> > new file mode 100644\n> > index 000000000000..b2af4df874df\n> > --- /dev/null\n> > +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-p\n> > +++ inctrl.yaml\n> > @@ -0,0 +1,217 @@\n> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2\n> > +---\n> > +$id:\n> > +http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.ya\n> > +ml#\n> > +$schema: http://devicetree.org/meta-schemas/core.yaml#\n> > +\n> > +title: StarFive JHB100 Peripheral-1 Pin Controller\n> > +\n> > +description: |\n> > + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.\n> > +\n> > + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2,\n> > + per0, per1, per2, per2pok, per3, adc0, adc1, emmc, and vga.\n> > + This document provides an overview of the \"per1\" pinctrl domain.\n> > +\n> > + The \"per1\" domain has a pin controller which provides\n> > + - function selection for GPIO pads.\n> > + - GPIO pad configuration.\n> > + - GPIO interrupt handling.\n> > +\n> > + In the Peripheral-1 Pin Controller, there are 36 multi-function\n> > + GPIO_PADs. Each of them can be multiplexed to several peripherals\n> > + through function selection. Each iopad has a maximum of up to 3\n> > + functions - 0, 1, and 2. Function 0 is the default function which is\n> > + generally the GPIO function. Function 1 and 2 are the alternate\n> > + functions or peripheral signals that can be routed to the iopad. The\n> function selection can be carried out by writing the function number to the\n> iopad function select register.\n> > + Each iopad is configurable with parameters such as input-enable,\n> > + internal pull-up/pull-down bias, drive strength, schmitt trigger, slew rate,\n> and debounce width.\n> > +\n> > + This domain contains 4 IO groups which support voltage levels 1.8V\n> > + and 3.3V gpioe-spi - comprises PAD_GPIO_C0 through PAD_GPIO_C4.\n> > + gpioe-qspi0 - comprises PAD_GPIO_C5 through PAD_GPIO_C11.\n> > + gpioe-qspi1 - comprises PAD_GPIO_C12 through PAD_GPIO_C19.\n> > + gpioe-qspi2 - comprises PAD_GPIO_C20 through PAD_GPIO_C27.\n> > +\n> > + Each of the above IO groups must be configured with a voltage\n> > + setting that matches the external voltage level provided to the IO group.\n> > +\n> > +maintainers:\n> > + - Alex Soo \n> > +\n> > +properties:\n> > + compatible:\n> > + items:\n> > + - const: starfive,jhb100-per1-pinctrl\n> > +\n> > + reg:\n> > + maxItems: 1\n> > +\n> > + clocks:\n> > + maxItems: 1\n> > +\n> > + resets:\n> > + maxItems: 1\n> > +\n> > + interrupts:\n> > + maxItems: 1\n> > +\n> > + interrupt-controller: true\n> > +\n> > + '#interrupt-cells':\n> > + const: 2\n> > +\n> > + gpio-controller: true\n> > +\n> > + '#gpio-cells':\n> > + const: 2\n> > +\n> > + gpio-ranges:\n> > + maxItems: 1\n> > +\n> > + gpio-line-names: true\n> > +\n> > + gpioe-spi-vref:\n> \n> Why are these custom properties required?\n> This sounds like the sort of information that could be gleaned from the\n> \"power-source\" property.\n\nThe voltage configuration here applies to multiple pin groups, making it less suitable to use power-source. \nIn patch 13, we defined a starfive,gmac-vsel property, which can be applied to individual pins. It might be \nmore appropriate to use power-source.\n\n> \n> > + description: |\n> > + Voltage reference value for the IO group \"gpioe-spi\"\n> > + 0: voltage reference value for 3.3V\n> > + 2: voltage reference value for 1.8V\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> > + enum: [0, 2]\n> > + default: 0\n> > +\n> > + gpioe-qspi0-vref:\n> > + description: |\n> > + Voltage reference value for the IO group \"gpioe-qspi0\"\n> > + 0: voltage reference value for 3.3V\n> > + 2: voltage reference value for 1.8V\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> > + enum: [0, 2]\n> > + default: 0\n> > +\n> > + gpioe-qspi1-vref:\n> > + description: |\n> > + Voltage reference value for the IO group \"gpioe-qspi1\"\n> > + 0: voltage reference value for 3.3V\n> > + 2: voltage reference value for 1.8V\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> > + enum: [0, 2]\n> > + default: 0\n> > +\n> > + gpioe-qspi2-vref:\n> > + description: |\n> > + Voltage reference value for the IO group \"gpioe-qspi2\"\n> > + 0: voltage reference value for 3.3V\n> > + 2: voltage reference value for 1.8V\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> > + enum: [0, 2]\n> > + default: 0\n> > +\n> > +patternProperties:\n> > + '-grp$':\n> > + type: object\n> > + additionalProperties: false\n> > + patternProperties:\n> > + '-pins$':\n> > + type: object\n> > + description: |\n> > + A pinctrl node should contain at least one subnode\n> representing the\n> > + pinctrl groups available in the domain. Each subnode will list\n> the\n> > + pins it needs, and how they should be configured, with regard\n> to\n> > + function selection, bias, input enable/disable, input schmitt\n> > + trigger enable/disable, slew-rate and drive strength.\n> > + allOf:\n> > + - $ref: /schemas/pinctrl/pincfg-node.yaml\n> > + - $ref: /schemas/pinctrl/pinmux-node.yaml\n> > + unevaluatedProperties: false\n> > +\n> > + properties:\n> > + pinmux:\n> > + description: |\n> > + The list of GPIOs and their function select.\n> > + The PINMUX macros are used to configure the\n> > + function selection.\n> \n> Why is the pinmux property needed?\n> Can you use pins and function instead?\n> \n> Looking at the defines that you have added, it appears that lots of defines for\n> the same peripheral share the same numerical values, suggesting that across\n> peripheral, all (or most) pins would share the same mux setting/\"function\n> select\", suggesting that pins/function would suffice.\n> \n> I'd like to see some justification for pinmux being the right solution here, like\n> the \"function select\" used by one peripheral being significantly different for\n> many of its pins.\n\nWe think that implementing this in the pinmux will be relatively simple. It avoids \nthe need to create a large number of mapping relationships in the driver, which \nsimplifies our driver implementation. I'm not sure if you'll find this explanation \nacceptable.\n\n> > +\n> > + bias-disable: true\n> > +\n> > + bias-pull-up:\n> > + type: boolean\n> > +\n> > + bias-pull-down:\n> > + type: boolean\n> > +\n> > + drive-strength:\n> > + enum: [ 2, 4, 8, 12 ]\n> > +\n> > + drive-strength-microamp:\n> > + enum: [ 2000, 4000, 8000, 12000 ]\n> > +\n> > + input-enable: true\n> > +\n> > + input-disable: true\n> > +\n> > + input-schmitt-enable: true\n> > +\n> > + input-schmitt-disable: true\n> > +\n> > + slew-rate:\n> > + enum: [ 0, 1 ]\n> > + default: 0\n> > + description: |\n> > + 0: slow (half frequency)\n> > + 1: fast\n> > +\n> > + starfive,debounce-width:\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> > + default: 0\n> > + description:\n> > + Debounce width 0 = Disabled, Others = 80ns*N stages\n> \n> This sounds like it should be called \"debounce-stages\".\n> \n> > +\n> > + starfive,drive-i2c-fast-mode:\n> > + type: boolean\n> > + description:\n> > + Enable I2C fast mode drive\n> > +\n> > + starfive,drive-i2c-fast-mode-plus:\n> > + type: boolean\n> > + description:\n> > + Enable I2C fast mode plus drive\n> > +\n> > + starfive,i2c-open-drain-pull-up-ohm:\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> \n> The unit of resistance is \"ohms\" in dt-schema, if you swap to that you won't\n> need the $ref.\n> \n> > + description:\n> > + open drain pull-up select\n> > + enum: [600, 900, 1200, 2000]\n> > + default: 600\n> > +\n> > +required:\n> > + - compatible\n> > + - reg\n> > + - resets\n> > + - interrupts\n> > + - interrupt-controller\n> > + - '#interrupt-cells'\n> > + - gpio-controller\n> > + - '#gpio-cells'\n> > + - gpio-ranges\n> > +\n> > +additionalProperties: false\n> > +\n> > +examples:\n> > + - |\n> > + soc {\n> > + #address-cells = <2>;\n> > + #size-cells = <2>;\n> > +\n> > + pinctrl_per1: pinctrl@11b42000 {\n> \n> Drop the label here, since there's no users.\n\nThis label is referenced in gpio-ranges.\n\n> \n> Cheers,\n> Conor.\n> \n> > + compatible = \"starfive,jhb100-per1-pinctrl\";\n> > + reg = <0x0 0x11b42000 0x0 0x800>;\n> > + resets = <&per1crg 0>;\n> > + interrupts = <61>;\n> > + interrupt-controller;\n> > + #interrupt-cells = <2>;\n> > + gpio-controller;\n> > + #gpio-cells = <2>;\n> > + gpio-ranges = <&pinctrl_per1 0 0 36>;\n> > + };\n> > + };\n> > --\n> > 2.25.1\n> >\n\nBest Regards,\nChanghuang","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=starfivetech.com;\n spf=pass smtp.mailfrom=starfivetech.com;\n arc=fail smtp.client-ip=139.219.17.121","i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=starfivetech.com; dmarc=pass action=none\n header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none"],"From":"Changhuang Liang ","To":"Conor Dooley ","CC":"Linus Walleij , Rob Herring ,\n\tKrzysztof Kozlowski , Conor Dooley ,\n\tEmil Renner Berthing , Paul Walmsley ,\n\tAlbert Ou , Palmer Dabbelt ,\n\tAlexandre Ghiti , Philipp Zabel ,\n\tBartosz Golaszewski , \"linux-gpio@vger.kernel.org\"\n\t, \"linux-kernel@vger.kernel.org\"\n\t, \"devicetree@vger.kernel.org\"\n\t, \"linux-riscv@lists.infradead.org\"\n\t, Lianfeng Ouyang\n\t","Subject":"Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","Thread-Topic":"[PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","Thread-Index":"AQHc09tvLatUK5oq3keSy4c9Ncpt5LXubvkAgAVF1NA=","Date":"Tue, 28 Apr 2026 01:28:05 +0000","Message-ID":"\n ","References":"<20260424111330.702272-1-changhuang.liang@starfivetech.com>\n <20260424111330.702272-12-changhuang.liang@starfivetech.com>\n <20260424-mumps-foothill-ef122c1029c0@spud>","In-Reply-To":"<20260424-mumps-foothill-ef122c1029c0@spud>","Accept-Language":"zh-CN, en-US","Content-Language":"zh-CN","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"quoted-printable","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"starfivetech.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"\n ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 29c23a8b-15b0-4a83-1ad0-08dea4c5658c","X-MS-Exchange-CrossTenant-originalarrivaltime":"28 Apr 2026 01:28:05.2278\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"06fe3fa3-1221-43d3-861b-5a4ee687a85c","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n AnxafjOrSPOCeAhUtTFGmlpT8/FL/C9FUPdFvkHQ16xQ2nZ/kMRxT+ScoboadLYhjIoUHL/B1f6z7/3Hfcq6ufCgYly9dryuMWxkYUC/vGY+Bo47vomN/tGoHydmJmGV","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"ZQ4PR01MB1153"}},{"id":3683391,"web_url":"http://patchwork.ozlabs.org/comment/3683391/","msgid":"","list_archive_url":null,"date":"2026-04-28T11:08:09","subject":"Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","submitter":{"id":92050,"url":"http://patchwork.ozlabs.org/api/people/92050/","name":"Linus Walleij","email":"linusw@kernel.org"},"content":"Hi Changhuang,\n\nthanks for your patch!\n\nOn Fri, Apr 24, 2026 at 1:14 PM Changhuang Liang\n wrote:\n\n> Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1) pinctrl\n> controller.\n>\n> Signed-off-by: Changhuang Liang \n(...)\n\n> + This domain contains 4 IO groups which support voltage levels 1.8V and 3.3V\n> + gpioe-spi - comprises PAD_GPIO_C0 through PAD_GPIO_C4.\n> + gpioe-qspi0 - comprises PAD_GPIO_C5 through PAD_GPIO_C11.\n> + gpioe-qspi1 - comprises PAD_GPIO_C12 through PAD_GPIO_C19.\n> + gpioe-qspi2 - comprises PAD_GPIO_C20 through PAD_GPIO_C27.\n> +\n> + Each of the above IO groups must be configured with a voltage setting that matches the external\n> + voltage level provided to the IO group.\n\nSo your hardware has groups and support some properties on the group level.\n\nSo expose these groups and make these properties configurable per group\ninstead of inventing per-group properties.\n\n> + gpioe-spi-vref:\n> + gpioe-qspi0-vref:\n> + gpioe-qspi1-vref:\n> + gpioe-qspi2-vref:\n\nCreate proper groups in the pin controller then use the\nstandard pincfg property power-source = <...>; for this.\n\nExample for a simple default hog:\n\npinctrl {\n /* Hog the QSPI pins */\n pinctrl-names = \"default\";\n pinctrl-0 = <&qspi_default>;\n\n qspi_default: pinctrl-qspi {\n config {\n groups = \"gpioe-qspi-pins\";\n power-source = <2>;\n };\n };\n};\n\nThe groups can be orthogonal to other pin handling, that's\nfine. Implement .pin_config_group_set in struct pinconf_ops.\n\n> + starfive,debounce-width:\n> + starfive,drive-i2c-fast-mode:\n> + starfive,drive-i2c-fast-mode-plus:\n> + starfive,i2c-open-drain-pull-up-ohm:\n\nI already adressed these in other review comments. Get rid of\nthem in favor of standard pinconfig bindings.\n\nYours,\nLinus Walleij","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=F+Ki5qsn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35694-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"F+Ki5qsn\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4dBs4Tddz1xrS\n\tfor ; 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Tue, 28 Apr 2026\n 04:08:20 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20260424111330.702272-1-changhuang.liang@starfivetech.com>\n <20260424111330.702272-12-changhuang.liang@starfivetech.com>","In-Reply-To":"<20260424111330.702272-12-changhuang.liang@starfivetech.com>","From":"Linus Walleij ","Date":"Tue, 28 Apr 2026 13:08:09 +0200","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AVHnY4IDxcIj36cpLzKrI1NZVFjYAH9TxKPvCzuHnuFYmrkebhBtVhuQTXFLwpQ","Message-ID":"\n ","Subject":"Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","To":"Changhuang Liang ","Cc":"Rob Herring , Krzysztof Kozlowski ,\n\tConor Dooley , Emil Renner Berthing ,\n Paul Walmsley ,\n\tAlbert Ou , Palmer Dabbelt ,\n\tAlexandre Ghiti , Philipp Zabel ,\n\tBartosz Golaszewski , linux-gpio@vger.kernel.org,\n linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-riscv@lists.infradead.org,\n\tLianfeng Ouyang ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3683667,"web_url":"http://patchwork.ozlabs.org/comment/3683667/","msgid":"<20260428-hardhat-both-1c9aa594a45a@spud>","list_archive_url":null,"date":"2026-04-28T18:51:09","subject":"Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","submitter":{"id":84372,"url":"http://patchwork.ozlabs.org/api/people/84372/","name":"Conor Dooley","email":"conor@kernel.org"},"content":"On Tue, Apr 28, 2026 at 01:28:05AM +0000, Changhuang Liang wrote:\n> > On Fri, Apr 24, 2026 at 04:13:21AM -0700, Changhuang Liang wrote:\n> > > Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1)\n> > > pinctrl controller.\n> > >\n> > > Signed-off-by: Changhuang Liang \n> > > + properties:\n> > > + pinmux:\n> > > + description: |\n> > > + The list of GPIOs and their function select.\n> > > + The PINMUX macros are used to configure the\n> > > + function selection.\n> > \n> > Why is the pinmux property needed?\n> > Can you use pins and function instead?\n> > \n> > Looking at the defines that you have added, it appears that lots of defines for\n> > the same peripheral share the same numerical values, suggesting that across\n> > peripheral, all (or most) pins would share the same mux setting/\"function\n> > select\", suggesting that pins/function would suffice.\n> > \n> > I'd like to see some justification for pinmux being the right solution here, like\n> > the \"function select\" used by one peripheral being significantly different for\n> > many of its pins.\n> \n> We think that implementing this in the pinmux will be relatively simple. It avoids \n> the need to create a large number of mapping relationships in the driver, which \n> simplifies our driver implementation. I'm not sure if you'll find this explanation \n> acceptable.\n\nI don't really see how pins + functions would require lots of \"mapping\nrelationships\". Instead of having\n+/* pinctrl_sys2 pad function selection */\n+#define FUNC_SYS2_UART_CTS\t\t\t\t1\n+#define FUNC_SYS2_UART_RTS\t\t\t\t1\n+#define FUNC_SYS2_UART_DCD\t\t\t\t1\n+#define FUNC_SYS2_UART_DSR\t\t\t\t1\n+#define FUNC_SYS2_UART_DTR\t\t\t\t1\n+#define FUNC_SYS2_UART_RI\t\t\t\t1\n+#define FUNC_SYS2_UART0_TX\t\t\t\t1\n+#define FUNC_SYS2_UART0_RX\t\t\t\t1\n+#define FUNC_SYS2_UART1_TX\t\t\t\t1\n+#define FUNC_SYS2_UART1_RX\t\t\t\t1\n+#define FUNC_SYS2_UART2_TX\t\t\t\t1\n+#define FUNC_SYS2_UART2_RX\t\t\t\t1\n+#define FUNC_SYS2_UART3_TX\t\t\t\t1\n+#define FUNC_SYS2_UART3_RX\t\t\t\t1\n+#define FUNC_SYS2_UART4_TX\t\t\t\t1\n+#define FUNC_SYS2_UART4_RX\t\t\t\t1\n+#define FUNC_SYS2_UART5_TX\t\t\t\t1\n+#define FUNC_SYS2_UART5_RX\t\t\t\t1\n+#define FUNC_SYS2_UART6_TX\t\t\t\t1\n+#define FUNC_SYS2_UART6_RX\t\t\t\t1\n+#define FUNC_SYS2_UART7_TX\t\t\t\t1\n+#define FUNC_SYS2_UART7_RX\t\t\t\t1\n+#define FUNC_SYS2_UART8_TX\t\t\t\t1\n+#define FUNC_SYS2_UART8_RX\t\t\t\t1\n+#define FUNC_SYS2_UART9_TX\t\t\t\t1\n+#define FUNC_SYS2_UART9_RX\t\t\t\t1\n+#define FUNC_SYS2_UART10_TX\t\t\t\t1\n+#define FUNC_SYS2_UART10_RX\t\t\t\t1\n+#define FUNC_SYS2_UART11_TX\t\t\t\t1\n+#define FUNC_SYS2_UART11_RX\t\t\t\t1\n+#define FUNC_SYS2_UART12_TX\t\t\t\t1\n+#define FUNC_SYS2_UART12_RX\t\t\t\t1\n+#define FUNC_SYS2_UART13_TX\t\t\t\t1\n+#define FUNC_SYS2_UART13_RX\t\t\t\t1\n+#define FUNC_SYS2_UART14_TX\t\t\t\t1\n+#define FUNC_SYS2_UART14_RX\t\t\t\t1\nyou just define a function called \"uart\" and have a simple map of\nthat string to the number 1. You end up with a single array with the\nrelationships, not lots.\n\nFrankly, pinmux just does not seem appropriate to me when it looks like\n90%+ of the pin mappings for a peripheral share the same function value.\nThere appears only to be a rare number of cases where that doesn't\napply, but that could be handled by having them represented by a\ndifferent group/pins node with a different function.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=gGsqMJQ3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35731-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"gGsqMJQ3\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4qMm628Zz1yHv\n\tfor ; Wed, 29 Apr 2026 04:53:40 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 3578E30BE8DA\n\tfor ; Tue, 28 Apr 2026 18:51:16 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 395B947CC6C;\n\tTue, 28 Apr 2026 18:51:15 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id ED94132939C;\n\tTue, 28 Apr 2026 18:51:14 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 6348FC2BCAF;\n\tTue, 28 Apr 2026 18:51:11 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777402275; cv=none;\n b=UtWxhuNftFzvQ96QU/NRkwWczqs81kA1bELopOHmLsCJib/Da2zkPhJGfj4TvPgT0tdLyDc8lCzakmzb5NqQdE27+9+OQ26aHtnbcjjh5ISbNRD0hrNiVwCE2WXCxU7KCEC8IWDfknyvNGIB3UhDgnsjhzysGXaPXarlBXrClQg=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777402275; c=relaxed/simple;\n\tbh=1seDTjn6972nfWjS0rEHA9YvmB2LMSwUbkkv4XJ/ipQ=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=IVQW4ovPwMb8drOnJFqpaWOfvY4KInkLT2ej/qj66IBhLG6YzLTyTM+yqo84y1sXwhMYnobGfsL9rKTiu+xrYlFFwpQcRstXKcgVXxJcr46POUIAGXFpb5PDZcjZuRI5zW5b0Pwc4EnykCdEIXfMeIE2OuWoJbxmehcvQpjQWmk=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=gGsqMJQ3; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777402274;\n\tbh=1seDTjn6972nfWjS0rEHA9YvmB2LMSwUbkkv4XJ/ipQ=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=gGsqMJQ3dXP21blxtK27vRWL3orDgvzaYg5b0vvG/JRAhzR4Kz9DqHk32KyhUcDB3\n\t C5oU6vXj5Np3HgxMkqbU2N5jkSIkF+UP1DVflUSIXcwGDfcEiHYleMjQp3r+463PUw\n\t an4Enwm8wFkHI90vonRB8OwaugryHKeuryhY65kw6WduN42Psyl4TqUjF/ucmNtnBz\n\t bLrY1ndTlyAJDoztXsOHMkm8c/trO4qf9/alcoNwH68+eXwHAJyfmzJaZFUBsY/rPv\n\t p2MA48sC8o1YtmCQcZsxuAqBa9JHSBy5LPJcdKwV8EKb5oG8DBh7tZPS2Jt8Ui6l0n\n\t otiO/4jX5ZEDw==","Date":"Tue, 28 Apr 2026 19:51:09 +0100","From":"Conor Dooley ","To":"Changhuang Liang ","Cc":"Linus Walleij , Rob Herring ,\n\tKrzysztof Kozlowski ,\n\tConor Dooley ,\n\tEmil Renner Berthing ,\n\tPaul Walmsley , Albert Ou ,\n\tPalmer Dabbelt ,\n\tAlexandre Ghiti ,\n\tPhilipp Zabel ,\n\tBartosz Golaszewski ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\t\"devicetree@vger.kernel.org\" ,\n\t\"linux-riscv@lists.infradead.org\" ,\n\tLianfeng Ouyang ","Subject":"Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add\n starfive,jhb100-per1-pinctrl","Message-ID":"<20260428-hardhat-both-1c9aa594a45a@spud>","References":"<20260424111330.702272-1-changhuang.liang@starfivetech.com>\n <20260424111330.702272-12-changhuang.liang@starfivetech.com>\n <20260424-mumps-foothill-ef122c1029c0@spud>\n ","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"xMbyPycYGBGKvOmn\"","Content-Disposition":"inline","In-Reply-To":"\n "}}]