[{"id":3682043,"web_url":"http://patchwork.ozlabs.org/comment/3682043/","msgid":"","list_archive_url":null,"date":"2026-04-24T13:58:26","subject":"Re: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to\n fix MMIO abort","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 24/4/26 22:18, Junjie Cao wrote:\n> Raise .impl.min_access_size from 4 to 8 in vtd_mem_ops so the memory\n> subsystem always widens guest accesses to 8 bytes before calling the\n> handler. This eliminates all 25 assert(size == 4) sites that crashed\n> QEMU on an 8-byte access to a 32-bit-only register.\n> \n> With size always 8, the if/else branches for 64-bit register pairs\n> collapse. A zero-extended 4-byte write to the low half is safe:\n> wmask protects read-only upper bits, and trigger functions re-read\n> the register file and guard on their action bits.\n> \n> The entry bounds check is relaxed to `addr >= DMAR_REG_SIZE` since\n> the widened size no longer reflects the guest access width; the\n> framework guarantees addr stays within the MemoryRegion. Default\n> branches fall back to vtd_get/set_long() when addr + 8 would exceed\n> the register file.\n> \n> Suggested-by: Philippe Mathieu-Daudé \n> Signed-off-by: Junjie Cao \n> ---\n> hw/i386/intel_iommu.c | 121 ++++++++----------------------------------\n> 1 file changed, 23 insertions(+), 98 deletions(-)\n> \n> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\n> index f395fa248c..4b25907778 100644\n> --- a/hw/i386/intel_iommu.c\n> +++ b/hw/i386/intel_iommu.c\n> @@ -3697,7 +3697,7 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n> \n> trace_vtd_reg_read(addr, size);\n> \n> - if (addr + size > DMAR_REG_SIZE) {\n> + if (addr >= DMAR_REG_SIZE) {\n> error_report_once(\"%s: MMIO over range: addr=0x%\" PRIx64\n> \" size=0x%x\", __func__, addr, size);\n> return (uint64_t)-1;\n> @@ -3707,13 +3707,9 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n> /* Root Table Address Register, 64-bit */\n> case DMAR_RTADDR_REG:\n> val = vtd_get_quad_raw(s, DMAR_RTADDR_REG);\n> - if (size == 4) {\n> - val = val & ((1ULL << 32) - 1);\n> - }\n> break;\n> \n> case DMAR_RTADDR_REG_HI:\n> - assert(size == 4);\n> val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;\n> break;\n> \n> @@ -3722,26 +3718,21 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n> val = s->iq |\n> (vtd_get_quad(s, DMAR_IQA_REG) &\n> (VTD_IQA_QS | VTD_IQA_DW_MASK));\n> - if (size == 4) {\n> - val = val & ((1ULL << 32) - 1);\n> - }\n> break;\n> \n> case DMAR_IQA_REG_HI:\n> - assert(size == 4);\n> val = s->iq >> 32;\n> break;\n> \n> case DMAR_PEUADDR_REG:\n> - assert(size == 4);\n\nDoes this device support unaligned accesses? (I doubt). Otherwise\naren't all these assert(size == 4) now g_assert_not_reached()?\n\n\n> @@ -4184,7 +4109,7 @@ static const MemoryRegionOps vtd_mem_ops = {\n> .write = vtd_mem_write,\n> .endianness = DEVICE_LITTLE_ENDIAN,\n> .impl = {\n> - .min_access_size = 4,\n> + .min_access_size = 8,\n> .max_access_size = 8,\n> },\n> .valid = {","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=bkB/INg/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2F1x3RHkz1xvV\n\tfor ; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::333;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3682458,"web_url":"http://patchwork.ozlabs.org/comment/3682458/","msgid":"<20260427012419.323362-1-junjie.cao@intel.com>","list_archive_url":null,"date":"2026-04-27T01:24:19","subject":"Re: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to\n fix MMIO abort","submitter":{"id":91537,"url":"http://patchwork.ozlabs.org/api/people/91537/","name":"Junjie Cao","email":"junjie.cao@intel.com"},"content":"Hi Philippe,\n\nThanks for the review and the good question.\n\nLooking at access_with_adjusted_size(), the _HI offsets (0x24, 0x2c, ...)\nand standalone 32-bit registers like DMAR_PEUADDR_REG (0xec) are\n4-byte-aligned but not 8-byte-aligned. An 8-byte guest access to them\nis indeed rejected by memory_region_access_valid (0xec & 7 != 0). But a\n4-byte access passes (0xec & 3 == 0), and the framework then widens size\nto 8 while keeping the original addr -- so the handler is still reached\nat these offsets.\n\nFor example, a guest 4-byte write to DMAR_PEUADDR_REG (0xec):\n\n 1. memory_region_access_valid: size=4, 0xec & 3 == 0 -> pass\n 2. access_with_adjusted_size: access_size = MAX(MIN(4,8),8) = 8\n 3. write_accessor calls vtd_mem_write(opaque, 0xec, val_zext, 8)\n 4. switch(addr) -> case DMAR_PEUADDR_REG -> vtd_set_long(s, addr, val)\n\nSo I believe these branches are still needed. Please let me know if\nI've missed something, or if you'd like any changes for v3.\n\nMany thanks,\nJunjie","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=l8CPUrJ9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3m9G073Lz1yJX\n\tfor ; Mon, 27 Apr 2026 11:25:52 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHAii-0008GB-Lw; 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a=\"78249170\"","E=Sophos;i=\"6.23,201,1770624000\"; d=\"scan'208\";a=\"78249170\"","E=Sophos;i=\"6.23,201,1770624000\"; d=\"scan'208\";a=\"257012724\""],"X-ExtLoop1":"1","From":"Junjie Cao ","To":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n qemu-devel@nongnu.org","Cc":"junjie.cao@intel.com, mst@redhat.com, jasowang@redhat.com,\n yi.l.liu@intel.com, clement.mathieu--drif@bull.com,\n zhenzhong.duan@intel.com","Subject":"Re: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to\n fix MMIO abort","Date":"Mon, 27 Apr 2026 09:24:19 +0800","Message-ID":"<20260427012419.323362-1-junjie.cao@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"","References":"<20260424201842.176953-1-junjie.cao@intel.com>\n <20260424201842.176953-2-junjie.cao@intel.com>\n ","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=192.198.163.15;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-39","X-Spam_score":"-4.0","X-Spam_bar":"----","X-Spam_report":"(-4.0 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1,\n DKIM_SIGNED=0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3682491,"web_url":"http://patchwork.ozlabs.org/comment/3682491/","msgid":"","list_archive_url":null,"date":"2026-04-27T05:23:41","subject":"RE: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to\n fix MMIO abort","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/people/81636/","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"content":">-----Original Message-----\n>From: Cao, Junjie \n>Subject: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to fix\n>MMIO abort\n>\n>Raise .impl.min_access_size from 4 to 8 in vtd_mem_ops so the memory\n>subsystem always widens guest accesses to 8 bytes before calling the\n>handler. This eliminates all 25 assert(size == 4) sites that crashed\n>QEMU on an 8-byte access to a 32-bit-only register.\n>\n>With size always 8, the if/else branches for 64-bit register pairs\n>collapse. A zero-extended 4-byte write to the low half is safe:\n>wmask protects read-only upper bits, and trigger functions re-read\n>the register file and guard on their action bits.\n>\n>The entry bounds check is relaxed to `addr >= DMAR_REG_SIZE` since\n>the widened size no longer reflects the guest access width; the\n>framework guarantees addr stays within the MemoryRegion. Default\n>branches fall back to vtd_get/set_long() when addr + 8 would exceed\n>the register file.\n>\n>Suggested-by: Philippe Mathieu-Daudé \n>Signed-off-by: Junjie Cao \n>---\n> hw/i386/intel_iommu.c | 121 ++++++++----------------------------------\n> 1 file changed, 23 insertions(+), 98 deletions(-)\n>\n>diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\n>index f395fa248c..4b25907778 100644\n>--- a/hw/i386/intel_iommu.c\n>+++ b/hw/i386/intel_iommu.c\n>@@ -3697,7 +3697,7 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr\n>addr, unsigned size)\n>\n> trace_vtd_reg_read(addr, size);\n>\n>- if (addr + size > DMAR_REG_SIZE) {\n>+ if (addr >= DMAR_REG_SIZE) {\n> error_report_once(\"%s: MMIO over range: addr=0x%\" PRIx64\n> \" size=0x%x\", __func__, addr, size);\n> return (uint64_t)-1;\n>@@ -3707,13 +3707,9 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr\n>addr, unsigned size)\n> /* Root Table Address Register, 64-bit */\n> case DMAR_RTADDR_REG:\n> val = vtd_get_quad_raw(s, DMAR_RTADDR_REG);\n>- if (size == 4) {\n>- val = val & ((1ULL << 32) - 1);\n>- }\n> break;\n>\n> case DMAR_RTADDR_REG_HI:\n>- assert(size == 4);\n> val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;\n> break;\n>\n>@@ -3722,26 +3718,21 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr\n>addr, unsigned size)\n> val = s->iq |\n> (vtd_get_quad(s, DMAR_IQA_REG) &\n> (VTD_IQA_QS | VTD_IQA_DW_MASK));\n>- if (size == 4) {\n>- val = val & ((1ULL << 32) - 1);\n>- }\n> break;\n>\n> case DMAR_IQA_REG_HI:\n>- assert(size == 4);\n> val = s->iq >> 32;\n> break;\n>\n> case DMAR_PEUADDR_REG:\n>- assert(size == 4);\n> val = vtd_get_long_raw(s, DMAR_PEUADDR_REG);\n> break;\n>\n> default:\n>- if (size == 4) {\n>- val = vtd_get_long(s, addr);\n>- } else {\n>+ if (addr + 8 <= DMAR_REG_SIZE) {\n> val = vtd_get_quad(s, addr);\n>+ } else {\n>+ val = vtd_get_long(s, addr);\n> }\n> }\n>\n>@@ -3755,7 +3746,7 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n>\n> trace_vtd_reg_write(addr, size, val);\n>\n>- if (addr + size > DMAR_REG_SIZE) {\n>+ if (addr >= DMAR_REG_SIZE) {\n> error_report_once(\"%s: MMIO over range: addr=0x%\" PRIx64\n> \" size=0x%x\", __func__, addr, size);\n> return;\n>@@ -3770,238 +3761,172 @@ static void vtd_mem_write(void *opaque, hwaddr\n>addr,\n>\n> /* Context Command Register, 64-bit */\n> case DMAR_CCMD_REG:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- vtd_handle_ccmd_write(s);\n>- }\n>+ vtd_set_quad(s, addr, val);\n>+ vtd_handle_ccmd_write(s);\n\nWill this cause wrong emulation when writing DMAR_CCMD_REG with 4 bytes size?\n\n> break;\n>\n> case DMAR_CCMD_REG_HI:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_ccmd_write(s);\n> break;\n>\n> /* IOTLB Invalidation Register, 64-bit */\n> case DMAR_IOTLB_REG:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- vtd_handle_iotlb_write(s);\n>- }\n>+ vtd_set_quad(s, addr, val);\n>+ vtd_handle_iotlb_write(s);\n> break;\n>\n> case DMAR_IOTLB_REG_HI:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_iotlb_write(s);\n> break;\n>\n> case DMAR_PEUADDR_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Invalidate Address Register, 64-bit */\n> case DMAR_IVA_REG:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- }\n>+ vtd_set_quad(s, addr, val);\n> break;\n>\n> case DMAR_IVA_REG_HI:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Fault Status Register, 32-bit */\n> case DMAR_FSTS_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_fsts_write(s);\n> break;\n>\n> /* Fault Event Control Register, 32-bit */\n> case DMAR_FECTL_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_fectl_write(s);\n> break;\n>\n> /* Fault Event Data Register, 32-bit */\n> case DMAR_FEDATA_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Fault Event Address Register, 32-bit */\n> case DMAR_FEADDR_REG:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- /*\n>- * While the register is 32-bit only, some guests (Xen...) write to\n>- * it with 64-bit.\n>- */\n>- vtd_set_quad(s, addr, val);\n>- }\n>+ vtd_set_quad(s, addr, val);\n> break;\n>\n> /* Fault Event Upper Address Register, 32-bit */\n> case DMAR_FEUADDR_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Protected Memory Enable Register, 32-bit */\n> case DMAR_PMEN_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Root Table Address Register, 64-bit */\n> case DMAR_RTADDR_REG:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- }\n>+ vtd_set_quad(s, addr, val);\n\nSame here, maybe also others, I didn't check all registers.\n\nThanks\nZhenzhong\n\n> break;\n>\n> case DMAR_RTADDR_REG_HI:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Invalidation Queue Tail Register, 64-bit */\n> case DMAR_IQT_REG:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- }\n>+ vtd_set_quad(s, addr, val);\n> vtd_handle_iqt_write(s);\n> break;\n>\n> case DMAR_IQT_REG_HI:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> /* 19:63 of IQT_REG is RsvdZ, do nothing here */\n> break;\n>\n> /* Invalidation Queue Address Register, 64-bit */\n> case DMAR_IQA_REG:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- }\n>+ vtd_set_quad(s, addr, val);\n> vtd_update_iq_dw(s);\n> break;\n>\n> case DMAR_IQA_REG_HI:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Invalidation Completion Status Register, 32-bit */\n> case DMAR_ICS_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_ics_write(s);\n> break;\n>\n> /* Invalidation Event Control Register, 32-bit */\n> case DMAR_IECTL_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_iectl_write(s);\n> break;\n>\n> /* Invalidation Event Data Register, 32-bit */\n> case DMAR_IEDATA_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Invalidation Event Address Register, 32-bit */\n> case DMAR_IEADDR_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Invalidation Event Upper Address Register, 32-bit */\n> case DMAR_IEUADDR_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> /* Fault Recording Registers, 128-bit */\n> case DMAR_FRCD_REG_0_0:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- }\n>+ vtd_set_quad(s, addr, val);\n> break;\n>\n> case DMAR_FRCD_REG_0_1:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> case DMAR_FRCD_REG_0_2:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- /* May clear bit 127 (Fault), update PPF */\n>- vtd_update_fsts_ppf(s);\n>- }\n>+ vtd_set_quad(s, addr, val);\n>+ /* May clear bit 127 (Fault), update PPF */\n>+ vtd_update_fsts_ppf(s);\n> break;\n>\n> case DMAR_FRCD_REG_0_3:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> /* May clear bit 127 (Fault), update PPF */\n> vtd_update_fsts_ppf(s);\n> break;\n>\n> case DMAR_IRTA_REG:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>- vtd_set_quad(s, addr, val);\n>- }\n>+ vtd_set_quad(s, addr, val);\n> break;\n>\n> case DMAR_IRTA_REG_HI:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> break;\n>\n> case DMAR_PRS_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_prs_write(s);\n> break;\n>\n> case DMAR_PECTL_REG:\n>- assert(size == 4);\n> vtd_set_long(s, addr, val);\n> vtd_handle_pectl_write(s);\n> break;\n>\n> default:\n>- if (size == 4) {\n>- vtd_set_long(s, addr, val);\n>- } else {\n>+ if (addr + 8 <= DMAR_REG_SIZE) {\n> vtd_set_quad(s, addr, val);\n>+ } else {\n>+ vtd_set_long(s, addr, val);\n> }\n> }\n> }\n>@@ -4184,7 +4109,7 @@ static const MemoryRegionOps vtd_mem_ops = {\n> .write = vtd_mem_write,\n> .endianness = DEVICE_LITTLE_ENDIAN,\n> .impl = {\n>- .min_access_size = 4,\n>+ .min_access_size = 8,\n> .max_access_size = 8,\n> },\n> .valid = {\n>--\n>2.43.0","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=G2tylU24;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","dkim=none (message not signed)\n header.d=none;dmarc=none action=none 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8tRwQNyPRt1vEMasRNj8U5REpuEvjlAgeaVyaL4L7osewp73QQQV8X8X+9lA82F1lp0l8cJzJof+mDS4LWOh1Oy9FsAa6EX0yiWxQd29VxI=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CYXPR11MB8662","X-OriginatorOrg":"intel.com","Received-SPF":"pass client-ip=192.198.163.17;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3684153,"web_url":"http://patchwork.ozlabs.org/comment/3684153/","msgid":"<20260430001607.3505699-1-junjie.cao@intel.com>","list_archive_url":null,"date":"2026-04-30T00:16:07","subject":"Re: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to\n fix MMIO abort","submitter":{"id":91537,"url":"http://patchwork.ozlabs.org/api/people/91537/","name":"Junjie Cao","email":"junjie.cao@intel.com"},"content":"Hi Zhenzhong,\n\nThanks for the careful review.\n\nYou are right that the code path has changed. With min_access_size=8\nthe handler always receives size=8, so a guest 4-byte write to a base\noffset calls vtd_set_quad() with a zero-extended value instead of\nvtd_set_long(). Two effects:\n\n\n1. Triggers called unconditionally\n\nCCMD_REG, IOTLB_REG, and FRCD_REG_0_2 originally guarded the\ntrigger on size==8. In v2 all three are still no-ops:\nvtd_handle_ccmd_write() and vtd_handle_iotlb_write() gate on\nICC/IVT (bit 63), which the zero-extended write just cleared\nthrough the wmask. For FRCD_REG_0_2, wmask is zero and the w1c\nbit 63 does not fire (val bit 63 = 0), so the register is\nunchanged.\n\n\n2. Upper writable bits cleared by zero-extended vtd_set_quad()\n\nWhere the upper 32-bit wmask is non-zero, zero-extended val clears\nthose bits:\n\n Register Offset Upper wmask Bits cleared\n CCMD_REG 0x28 0xe0000003 ICC, CIRG, 33:32\n IOTLB_REG 0xf8 0xb003ffff IVT, IIRG, DID\n RTADDR_REG 0x20 0xffffffff address 63:32\n IQA_REG 0x90 0xffffffff address 63:32\n IVA_REG 0xf0 0xffffffff address 63:32\n IRTA_REG 0xb8 0xffffffff address 63:32\n\n (IQT_REG, FRCD_0_0, and FRCD_0_2 have upper wmask = 0 -- safe.)\n\nThis is safe because a guest must program the full register before\nthe value is consumed: CCMD/IOTLB fields are set before the action\nbit (ICC/IVT) in the high-half write; RTADDR, IQA, and IRTA are\nlatched only when a GCMD enable bit (SRTP/QIE/SIRTP) fires; IVA is\nread when IOTLB invalidation triggers via IVT.\n\nHowever, a read-back between the low-half and high-half writes\nwould observe zeroed upper bits -- a real behavioral difference.\n\n\nTwo possible paths\n\n(a) Keep v2 as-is, add comments documenting the safety argument\n above.\n\n(b) Stay with min_access_size=4. Simply remove all 25 asserts.\n 21 sit at non-8-aligned offsets -- unreachable by any 8-byte\n guest access (alignment check rejects them). The remaining 4\n at 8-aligned offsets (FECTL 0x38, IECTL 0xa0, IEADDR 0xa8,\n PECTL 0xe0) fall through to vtd_set_long() which implicitly\n truncates the value -- safe and no semantic change. All\n existing size branches in 64-bit register pairs are preserved.\n\nAs I see it, both approaches are correct; (a) is simpler but\nchanges observable semantics in an edge case, (b) is conservative\nwith zero semantic change. That said, I am happy to hear any other\nsuggestions.\n\nThanks,\nJunjie","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=ieMRsnnA;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Mnx6lWSz1yHZ\n\tfor ; Thu, 30 Apr 2026 02:14:44 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wI7Xw-0004CK-VY; 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a=\"82020309\"","E=Sophos;i=\"6.23,206,1770624000\"; d=\"scan'208\";a=\"82020309\"","E=Sophos;i=\"6.23,206,1770624000\"; d=\"scan'208\";a=\"257644736\""],"X-ExtLoop1":"1","From":"Junjie Cao ","To":"zhenzhong.duan@intel.com","Cc":"qemu-devel@nongnu.org, mst@redhat.com, jasowang@redhat.com,\n yi.l.liu@intel.com, clement.mathieu--drif@bull.com, philmd@linaro.org,\n Junjie Cao ","Subject":"Re: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to\n fix MMIO abort","Date":"Thu, 30 Apr 2026 08:16:07 +0800","Message-ID":"<20260430001607.3505699-1-junjie.cao@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"\n ","References":"<20260424201842.176953-1-junjie.cao@intel.com>\n <20260424201842.176953-2-junjie.cao@intel.com>\n ","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.15;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-24","X-Spam_score":"-2.5","X-Spam_bar":"--","X-Spam_report":"(-2.5 / 5.0 requ) BAYES_00=-1.9, DATE_IN_FUTURE_06_12=1.947,\n DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1,\n DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3684531,"web_url":"http://patchwork.ozlabs.org/comment/3684531/","msgid":"","list_archive_url":null,"date":"2026-04-30T08:31:01","subject":"RE: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to\n fix MMIO abort","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/people/81636/","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"content":">-----Original Message-----\n>From: Cao, Junjie \n>Subject: Re: [PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to fix\n>MMIO abort\n>\n>Hi Zhenzhong,\n>\n>Thanks for the careful review.\n>\n>You are right that the code path has changed. With min_access_size=8\n>the handler always receives size=8, so a guest 4-byte write to a base\n>offset calls vtd_set_quad() with a zero-extended value instead of\n>vtd_set_long(). Two effects:\n>\n>\n>1. Triggers called unconditionally\n>\n>CCMD_REG, IOTLB_REG, and FRCD_REG_0_2 originally guarded the\n>trigger on size==8. In v2 all three are still no-ops:\n>vtd_handle_ccmd_write() and vtd_handle_iotlb_write() gate on\n>ICC/IVT (bit 63), which the zero-extended write just cleared\n>through the wmask. For FRCD_REG_0_2, wmask is zero and the w1c\n>bit 63 does not fire (val bit 63 = 0), so the register is\n>unchanged.\n>\n>\n>2. Upper writable bits cleared by zero-extended vtd_set_quad()\n>\n>Where the upper 32-bit wmask is non-zero, zero-extended val clears\n>those bits:\n>\n> Register Offset Upper wmask Bits cleared\n> CCMD_REG 0x28 0xe0000003 ICC, CIRG, 33:32\n> IOTLB_REG 0xf8 0xb003ffff IVT, IIRG, DID\n> RTADDR_REG 0x20 0xffffffff address 63:32\n> IQA_REG 0x90 0xffffffff address 63:32\n> IVA_REG 0xf0 0xffffffff address 63:32\n> IRTA_REG 0xb8 0xffffffff address 63:32\n>\n> (IQT_REG, FRCD_0_0, and FRCD_0_2 have upper wmask = 0 -- safe.)\n>\n>This is safe because a guest must program the full register before\n>the value is consumed: CCMD/IOTLB fields are set before the action\n>bit (ICC/IVT) in the high-half write; RTADDR, IQA, and IRTA are\n>latched only when a GCMD enable bit (SRTP/QIE/SIRTP) fires; IVA is\n>read when IOTLB invalidation triggers via IVT.\n>\n>However, a read-back between the low-half and high-half writes\n>would observe zeroed upper bits -- a real behavioral difference.\n>\n>\n>Two possible paths\n>\n>(a) Keep v2 as-is, add comments documenting the safety argument\n> above.\n\nThis is risky, there is no guarantee that trigger bit is in upper register.\n\n>\n>(b) Stay with min_access_size=4. Simply remove all 25 asserts.\n> 21 sit at non-8-aligned offsets -- unreachable by any 8-byte\n> guest access (alignment check rejects them). The remaining 4\n> at 8-aligned offsets (FECTL 0x38, IECTL 0xa0, IEADDR 0xa8,\n> PECTL 0xe0) fall through to vtd_set_long() which implicitly\n> truncates the value -- safe and no semantic change. All\n> existing size branches in 64-bit register pairs are preserved.\n\nThis makes sense. I didn't find what happen about 8bytes access on\n4bytes register in VTD spec, but I think at least we can print a\nwarning for the remaining 4 registers, instead of silently truncate.\n\nThanks\nZhenzhong\n\n>\n>As I see it, both approaches are correct; (a) is simpler but\n>changes observable semantics in an edge case, (b) is conservative\n>with zero semantic change. That said, I am happy to hear any other\n>suggestions.\n>\n>Thanks,\n>Junjie","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=DqdfepYm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=intel.com;"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5nTG2Vc2z1yHZ\n\tfor ; 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