[{"id":3682032,"web_url":"http://patchwork.ozlabs.org/comment/3682032/","msgid":"<5794be46-6755-4216-a57b-9a94172ec2b3@linaro.org>","list_archive_url":null,"date":"2026-04-24T13:17:38","subject":"Re: [PATCH 3/4] target/riscv: Support raising misaligned exceptions\n for vector loads/stores","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/24/26 20:27, frank.chang@sifive.com wrote:\n> --- a/target/riscv/insn_trans/trans_rvv.c.inc\n> +++ b/target/riscv/insn_trans/trans_rvv.c.inc\n> @@ -1190,9 +1190,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,\n> * Update vstart with the number of processed elements.\n> * Use the helper function if either:\n> * - vstart is not 0.\n> + * - Zicclsm is disabled, so misaligned accesses could trap.\n> */\n> \n> - bool use_helper_fn = !s->vstart_eq_zero;\n> + bool use_helper_fn = !s->vstart_eq_zero || !s->cfg_ptr->ext_zicclsm;\n> \n> if (!use_helper_fn) {\n> uint32_t size = s->cfg_ptr->vlenb * nf;\n\nThere is a whole set of MO_ALIGN_* values you can use to select the alignment of the \nvector element:\n\n log2_esz << MO_ASHIFT\n\nfor log2_esz <= 6 (aka MO_ALIGN_64).\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=X0uu4gkT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::102d;\n envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3682033,"web_url":"http://patchwork.ozlabs.org/comment/3682033/","msgid":"<058f177b-b8ab-4fb1-9998-ba21b559a30e@linaro.org>","list_archive_url":null,"date":"2026-04-24T13:20:44","subject":"Re: [PATCH 3/4] target/riscv: Support raising misaligned exceptions\n for vector loads/stores","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/24/26 20:27, frank.chang@sifive.com wrote:\n> +static MemOpIdx vext_make_memop_idx(CPURISCVState *env, size_t size)\n> +{\n> + int mmu_idx = riscv_env_mmu_index(env, false);\n> + MemOp memop;\n> +\n> + switch (size) {\n> + case 1:\n> + memop = MO_UB;\n> + break;\n> + case 2:\n> + memop = MO_LEUW;\n> + break;\n> + case 4:\n> + memop = MO_LEUL;\n> + break;\n> + case 8:\n> + memop = MO_LEUQ;\n> + break;\n> + default:\n> + g_assert_not_reached();\n> + }\n memop = size_memop(size) | mo_endian_env(env);\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=FccYf2Gr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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