[{"id":3681596,"web_url":"http://patchwork.ozlabs.org/comment/3681596/","msgid":"<923468b3-2bba-49b8-b6f9-69062e81f88a@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-23T17:43:57","subject":"Re: [PATCH 11/16] target/arm: Only set CPU_INTERRUPT_EXITTB for TCG","submitter":{"id":93152,"url":"http://patchwork.ozlabs.org/api/people/93152/","name":"Pierrick Bouvier","email":"pierrick.bouvier@oss.qualcomm.com"},"content":"On 4/23/2026 10:02 AM, Philippe Mathieu-Daudé wrote:\n> Commit 34c45d53026 (\"target-arm: kvm - re-inject guest debug\n> exceptions\") removed CPU_INTERRUPT_EXITTB from KVM, but it\n> also appears on HVF. Better to restrict it to TCG.\n> \n> Suggested-by: Richard Henderson \n> Signed-off-by: Philippe Mathieu-Daudé \n> Reviewed-by: Richard Henderson \n> Reviewed-by: Pierrick Bouvier \n> Message-Id: <20250630130937.3487-2-philmd@linaro.org>\n> ---\n> target/arm/helper.c | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n> \n\nReviewed-by: Pierrick Bouvier ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=oIuUIvxU;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=a6IjWbJD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1k4K2JwDz1yDD\n\tfor ; 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