[{"id":3681398,"web_url":"http://patchwork.ozlabs.org/comment/3681398/","msgid":"<5666c107-0033-4f67-9fcb-dd404886252b@kaod.org>","list_archive_url":null,"date":"2026-04-23T11:45:17","subject":"Re: [PATCH v4 08/17] hw/usb/hcd-ehci: Change descriptor addresses to\n 64-bit with migration compatibility","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/","name":"Cédric Le Goater","email":"clg@kaod.org"},"content":"Hello Jamin,\n\nOn 4/23/26 07:18, Jamin Lin wrote:\n> Change internal EHCI descriptor addresses from uint32_t to uint64_t.\n> \n> The following fields are updated:\n> - EHCIPacket::qtdaddr\n> - EHCIQueue::{qhaddr, qtdaddr}\n> - EHCIState::{a_fetch_addr, p_fetch_addr}\n> \n> Update get_dwords() and put_dwords() to take 64-bit addresses and\n> propagate the type change through the descriptor traversal paths.\n> \n> Adjust NLPTR_GET() to operate on 64-bit values:\n> \n> #define NLPTR_GET(x) ((x) & ~0x1fULL)\n> \n> so that link pointer masking works correctly when descriptor\n> addresses exceed 32-bit space. The previous mask (0xffffffe0)\n> implicitly truncated addresses to 32 bits.\n> \n> This patch does not change the on-wire descriptor layout yet.\n> It only removes the internal 32-bit address limit and prepares\n> for later patches that will add full 64-bit QH/qTD/iTD/siTD support.\n> \n> Update the EHCI trace-events prototypes for QH, qTD, iTD, and siTD to\n> use uint64_t for the address argument and print it with PRIx64. This\n> ensures full 64-bit addresses are shown in trace output and improves\n> debugging of queue heads and transfer descriptors.\n> \n> Migration compatibility:\n> \n> To preserve backward migration compatibility, keep the legacy 32-bit\n> fetch address fields (a_fetch_addr_32, p_fetch_addr_32) alongside the\n> new 64-bit fields.\n> \n> Migration format is selected using a machine compat property\n> \"x-migrate-fetch-addr-64bit\":\n> \n> - Old machine types migrate 32-bit fetch addresses\n> - New machine types migrate full 64-bit fetch addresses\n> \n> This is implemented using VMSTATE_UINT32_TEST() and\n> VMSTATE_UINT64_TEST() so that only the appropriate format is migrated.\n> \n> In pre_save, the 32-bit shadow fields are populated when migrating\n> to old machine types. In post_load, the 32-bit values are restored\n> into the 64-bit fields when loading old migration streams.\n> \n> No functional change.\n> \n> Signed-off-by: Jamin Lin \n> Reviewed-by: Philippe Mathieu-Daudé \n\nThis patch was reworked significantly to handle migration and I don't\nthink Philippe's Reviewed-by stands anymore.\n\nCould you please explain how you tested ? QEMU command lines, which\nOS, etc. ?\n\nThanks,\n\nC.\n\n> ---\n> hw/usb/hcd-ehci.h | 17 +++++++----\n> hw/core/machine.c | 2 ++\n> hw/usb/hcd-ehci.c | 72 ++++++++++++++++++++++++++++++++-------------\n> hw/usb/trace-events | 24 +++++++--------\n> 4 files changed, 76 insertions(+), 39 deletions(-)\n> \n> diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\n> index d038ee1e31..3acbddfc5c 100644\n> --- a/hw/usb/hcd-ehci.h\n> +++ b/hw/usb/hcd-ehci.h\n> @@ -208,7 +208,7 @@ struct EHCIPacket {\n> QTAILQ_ENTRY(EHCIPacket) next;\n> \n> EHCIqtd qtd; /* copy of current QTD (being worked on) */\n> - uint32_t qtdaddr; /* address QTD read from */\n> + uint64_t qtdaddr; /* address QTD read from */\n> \n> USBPacket packet;\n> QEMUSGList sgl;\n> @@ -229,8 +229,8 @@ struct EHCIQueue {\n> * when guest removes an entry (doorbell, handshake sequence)\n> */\n> EHCIqh qh; /* copy of current QH (being worked on) */\n> - uint32_t qhaddr; /* address QH read from */\n> - uint32_t qtdaddr; /* address QTD read from */\n> + uint64_t qhaddr; /* address QH read from */\n> + uint64_t qtdaddr; /* address QTD read from */\n> int last_pid; /* pid of last packet executed */\n> USBDevice *dev;\n> QTAILQ_HEAD(, EHCIPacket) packets;\n> @@ -256,6 +256,7 @@ struct EHCIState {\n> \n> /* properties */\n> uint32_t maxframes;\n> + bool migrate_fetch_addr_64bit;\n> \n> /*\n> * EHCI spec version 1.0 Section 2.3\n> @@ -294,8 +295,10 @@ struct EHCIState {\n> EHCIQueueHead pqueues;\n> \n> /* which address to look at next */\n> - uint32_t a_fetch_addr;\n> - uint32_t p_fetch_addr;\n> + uint32_t a_fetch_addr_32;\n> + uint32_t p_fetch_addr_32;\n> + uint64_t a_fetch_addr;\n> + uint64_t p_fetch_addr;\n> \n> USBPacket ipacket;\n> QEMUSGList isgl;\n> @@ -308,7 +311,9 @@ struct EHCIState {\n> };\n> \n> #define DEFINE_EHCI_COMMON_PROPERTIES(_state) \\\n> - DEFINE_PROP_UINT32(\"maxframes\", _state, ehci.maxframes, 128)\n> + DEFINE_PROP_UINT32(\"maxframes\", _state, ehci.maxframes, 128), \\\n> + DEFINE_PROP_BOOL(\"x-migrate-fetch-addr-64bit\", _state, \\\n> + ehci.migrate_fetch_addr_64bit, true)\n> \n> extern const VMStateDescription vmstate_ehci;\n> \n> diff --git a/hw/core/machine.c b/hw/core/machine.c\n> index 0aa77a57e9..e77400c7ab 100644\n> --- a/hw/core/machine.c\n> +++ b/hw/core/machine.c\n> @@ -41,6 +41,8 @@\n> GlobalProperty hw_compat_10_2[] = {\n> { \"scsi-block\", \"migrate-pr\", \"off\" },\n> { \"isa-cirrus-vga\", \"global-vmstate\", \"true\" },\n> + { \"sysbus-ehci-usb\", \"x-migrate-fetch-addr-64bit\", \"off\" },\n> + { \"pci-ehci-usb\", \"x-migrate-fetch-addr-64bit\", \"off\" },\n> };\n> const size_t hw_compat_10_2_len = G_N_ELEMENTS(hw_compat_10_2);\n> \n> diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\n> index 28a60e4c1a..0c8bdb48ad 100644\n> --- a/hw/usb/hcd-ehci.c\n> +++ b/hw/usb/hcd-ehci.c\n> @@ -72,7 +72,7 @@ typedef enum {\n> } EHCI_STATES;\n> \n> /* macros for accessing fields within next link pointer entry */\n> -#define NLPTR_GET(x) ((x) & 0xffffffe0)\n> +#define NLPTR_GET(x) ((x) & ~0x1fULL)\n> #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)\n> #define NLPTR_TBIT(x) ((x) & 1) /* 1=invalid, 0=valid */\n> \n> @@ -287,7 +287,7 @@ static int ehci_get_state(EHCIState *s, int async)\n> return async ? s->astate : s->pstate;\n> }\n> \n> -static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)\n> +static void ehci_set_fetch_addr(EHCIState *s, int async, uint64_t addr)\n> {\n> if (async) {\n> s->a_fetch_addr = addr;\n> @@ -296,7 +296,7 @@ static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)\n> }\n> }\n> \n> -static int ehci_get_fetch_addr(EHCIState *s, int async)\n> +static uint64_t ehci_get_fetch_addr(EHCIState *s, int async)\n> {\n> return async ? s->a_fetch_addr : s->p_fetch_addr;\n> }\n> @@ -373,7 +373,7 @@ static inline bool ehci_periodic_enabled(EHCIState *s)\n> }\n> \n> /* Get an array of dwords from main memory */\n> -static inline int get_dwords(EHCIState *ehci, uint32_t addr,\n> +static inline int get_dwords(EHCIState *ehci, uint64_t addr,\n> uint32_t *buf, int num)\n> {\n> int i;\n> @@ -395,7 +395,7 @@ static inline int get_dwords(EHCIState *ehci, uint32_t addr,\n> }\n> \n> /* Put an array of dwords in to main memory */\n> -static inline int put_dwords(EHCIState *ehci, uint32_t addr,\n> +static inline int put_dwords(EHCIState *ehci, uint64_t addr,\n> uint32_t *buf, int num)\n> {\n> int i;\n> @@ -549,7 +549,7 @@ static void ehci_free_packet(EHCIPacket *p)\n> \n> /* queue management */\n> \n> -static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)\n> +static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint64_t addr, int async)\n> {\n> EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;\n> EHCIQueue *q;\n> @@ -622,7 +622,7 @@ static void ehci_free_queue(EHCIQueue *q, const char *warn)\n> g_free(q);\n> }\n> \n> -static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,\n> +static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint64_t addr,\n> int async)\n> {\n> EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;\n> @@ -1135,7 +1135,7 @@ static void ehci_flush_qh(EHCIQueue *q)\n> {\n> uint32_t *qh = (uint32_t *) &q->qh;\n> uint32_t dwords = sizeof(EHCIqh) >> 2;\n> - uint32_t addr = NLPTR_GET(q->qhaddr);\n> + uint64_t addr = NLPTR_GET(q->qhaddr);\n> \n> put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);\n> }\n> @@ -1406,12 +1406,13 @@ static int ehci_execute(EHCIPacket *p, const char *action)\n> /* 4.7.2 */\n> static int ehci_process_itd(EHCIState *ehci,\n> EHCIitd *itd,\n> - uint32_t addr)\n> + uint64_t addr)\n> {\n> USBDevice *dev;\n> USBEndpoint *ep;\n> uint32_t i, len, pid, dir, devaddr, endp;\n> - uint32_t pg, off, ptr1, ptr2, max, mult;\n> + uint32_t pg, off, max, mult;\n> + uint64_t ptr1, ptr2;\n> \n> ehci->periodic_sched_active = PERIODIC_ACTIVE;\n> \n> @@ -1528,7 +1529,7 @@ static int ehci_state_waitlisthead(EHCIState *ehci, int async)\n> EHCIqh qh;\n> int i = 0;\n> int again = 0;\n> - uint32_t entry = ehci->asynclistaddr;\n> + uint64_t entry = ehci->asynclistaddr;\n> \n> /* set reclamation flag at start event (4.8.6) */\n> if (async) {\n> @@ -1578,7 +1579,7 @@ out:\n> static int ehci_state_fetchentry(EHCIState *ehci, int async)\n> {\n> int again = 0;\n> - uint32_t entry = ehci_get_fetch_addr(ehci, async);\n> + uint64_t entry = ehci_get_fetch_addr(ehci, async);\n> \n> if (NLPTR_TBIT(entry)) {\n> ehci_set_state(ehci, async, EST_ACTIVE);\n> @@ -1611,7 +1612,7 @@ static int ehci_state_fetchentry(EHCIState *ehci, int async)\n> default:\n> /* TODO: handle FSTN type */\n> qemu_log_mask(LOG_GUEST_ERROR,\n> - \"FETCHENTRY: entry at 0x%x is of type %u \"\n> + \"FETCHENTRY: entry at %\" PRIx64 \"is of type %\" PRIu64\n> \"which is not supported yet\\n\",\n> entry, NLPTR_TYPE_GET(entry));\n> return -1;\n> @@ -1623,7 +1624,7 @@ out:\n> \n> static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)\n> {\n> - uint32_t entry;\n> + uint64_t entry;\n> EHCIQueue *q;\n> EHCIqh qh;\n> \n> @@ -1712,7 +1713,7 @@ out:\n> \n> static int ehci_state_fetchitd(EHCIState *ehci, int async)\n> {\n> - uint32_t entry;\n> + uint64_t entry;\n> EHCIitd itd;\n> \n> assert(!async);\n> @@ -1738,7 +1739,7 @@ static int ehci_state_fetchitd(EHCIState *ehci, int async)\n> \n> static int ehci_state_fetchsitd(EHCIState *ehci, int async)\n> {\n> - uint32_t entry;\n> + uint64_t entry;\n> EHCIsitd sitd;\n> \n> assert(!async);\n> @@ -1802,7 +1803,7 @@ static int ehci_state_fetchqtd(EHCIQueue *q)\n> EHCIqtd qtd;\n> EHCIPacket *p;\n> int again = 1;\n> - uint32_t addr;\n> + uint64_t addr;\n> \n> addr = NLPTR_GET(q->qtdaddr);\n> if (get_dwords(q->ehci, addr + 8, &qtd.token, 1) < 0) {\n> @@ -1885,7 +1886,7 @@ static int ehci_fill_queue(EHCIPacket *p)\n> USBEndpoint *ep = p->packet.ep;\n> EHCIQueue *q = p->queue;\n> EHCIqtd qtd = p->qtd;\n> - uint32_t qtdaddr;\n> + uint64_t qtdaddr;\n> \n> for (;;) {\n> if (NLPTR_TBIT(qtd.next) != 0) {\n> @@ -2008,7 +2009,8 @@ static int ehci_state_executing(EHCIQueue *q)\n> static int ehci_state_writeback(EHCIQueue *q)\n> {\n> EHCIPacket *p = QTAILQ_FIRST(&q->packets);\n> - uint32_t *qtd, addr;\n> + uint32_t *qtd;\n> + uint64_t addr;\n> int again = 0;\n> \n> /* Write back the QTD from the QH area */\n> @@ -2414,6 +2416,18 @@ static USBBusOps ehci_bus_ops_standalone = {\n> .wakeup_endpoint = ehci_wakeup_endpoint,\n> };\n> \n> +static bool ehci_fetch_addr_64_needed(void *opaque, int version_id)\n> +{\n> + EHCIState *s = opaque;\n> +\n> + return s->migrate_fetch_addr_64bit;\n> +}\n> +\n> +static bool ehci_fetch_addr_32_needed(void *opaque, int version_id)\n> +{\n> + return !ehci_fetch_addr_64_needed(opaque, version_id);\n> +}\n> +\n> static int usb_ehci_pre_save(void *opaque)\n> {\n> EHCIState *ehci = opaque;\n> @@ -2424,6 +2438,11 @@ static int usb_ehci_pre_save(void *opaque)\n> ehci->last_run_ns -= (ehci->frindex - new_frindex) * UFRAME_TIMER_NS;\n> ehci->frindex = new_frindex;\n> \n> + if (!ehci->migrate_fetch_addr_64bit) {\n> + ehci->a_fetch_addr_32 = ehci->a_fetch_addr;\n> + ehci->p_fetch_addr_32 = ehci->p_fetch_addr;\n> + }\n> +\n> return 0;\n> }\n> \n> @@ -2444,6 +2463,11 @@ static int usb_ehci_post_load(void *opaque, int version_id)\n> }\n> }\n> \n> + if (!s->migrate_fetch_addr_64bit) {\n> + s->a_fetch_addr = s->a_fetch_addr_32;\n> + s->p_fetch_addr = s->p_fetch_addr_32;\n> + }\n> +\n> return 0;\n> }\n> \n> @@ -2504,8 +2528,14 @@ const VMStateDescription vmstate_ehci = {\n> /* schedule state */\n> VMSTATE_UINT32(astate, EHCIState),\n> VMSTATE_UINT32(pstate, EHCIState),\n> - VMSTATE_UINT32(a_fetch_addr, EHCIState),\n> - VMSTATE_UINT32(p_fetch_addr, EHCIState),\n> + VMSTATE_UINT32_TEST(a_fetch_addr_32, EHCIState,\n> + ehci_fetch_addr_32_needed),\n> + VMSTATE_UINT32_TEST(p_fetch_addr_32, EHCIState,\n> + ehci_fetch_addr_32_needed),\n> + VMSTATE_UINT64_TEST(a_fetch_addr, EHCIState,\n> + ehci_fetch_addr_64_needed),\n> + VMSTATE_UINT64_TEST(p_fetch_addr, EHCIState,\n> + ehci_fetch_addr_64_needed),\n> VMSTATE_END_OF_LIST()\n> }\n> };\n> diff --git a/hw/usb/trace-events b/hw/usb/trace-events\n> index 0d4318dcf1..8c90688bb3 100644\n> --- a/hw/usb/trace-events\n> +++ b/hw/usb/trace-events\n> @@ -86,15 +86,15 @@ usb_ehci_portsc_write(uint32_t addr, uint32_t port, uint32_t val) \"wr mmio 0x%04\n> usb_ehci_portsc_change(uint32_t addr, uint32_t port, uint32_t new, uint32_t old) \"ch mmio 0x%04x [port %d] = 0x%x (old: 0x%x)\"\n> usb_ehci_usbsts(const char *sts, int state) \"usbsts %s %d\"\n> usb_ehci_state(const char *schedule, const char *state) \"%s schedule %s\"\n> -usb_ehci_qh_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t c_qtd, uint32_t n_qtd, uint32_t a_qtd) \"q %p - QH @ 0x%08x: next 0x%08x qtds 0x%08x,0x%08x,0x%08x\"\n> -usb_ehci_qh_fields(uint32_t addr, int rl, int mplen, int eps, int ep, int devaddr) \"QH @ 0x%08x - rl %d, mplen %d, eps %d, ep %d, dev %d\"\n> -usb_ehci_qh_bits(uint32_t addr, int c, int h, int dtc, int i) \"QH @ 0x%08x - c %d, h %d, dtc %d, i %d\"\n> +usb_ehci_qh_ptrs(void *q, uint64_t addr, uint32_t nxt, uint32_t c_qtd, uint32_t n_qtd, uint32_t a_qtd) \"q %p - QH @ 0x%\" PRIx64 \": next 0x%08x qtds 0x%08x,0x%08x,0x%08x\"\n> +usb_ehci_qh_fields(uint64_t addr, int rl, int mplen, int eps, int ep, int devaddr) \"QH @ 0x%\" PRIx64 \" - rl %d, mplen %d, eps %d, ep %d, dev %d\"\n> +usb_ehci_qh_bits(uint64_t addr, int c, int h, int dtc, int i) \"QH @ 0x%\" PRIx64 \" - c %d, h %d, dtc %d, i %d\"\n> usb_ehci_qh_tbytes(uint32_t tbytes) \"updating tbytes to %d\"\n> -usb_ehci_qtd_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t altnext) \"q %p - QTD @ 0x%08x: next 0x%08x altnext 0x%08x\"\n> -usb_ehci_qtd_fields(uint32_t addr, int tbytes, int cpage, int cerr, int pid) \"QTD @ 0x%08x - tbytes %d, cpage %d, cerr %d, pid %d\"\n> -usb_ehci_qtd_bits(uint32_t addr, int ioc, int active, int halt, int babble, int xacterr) \"QTD @ 0x%08x - ioc %d, active %d, halt %d, babble %d, xacterr %d\"\n> -usb_ehci_itd(uint32_t addr, uint32_t nxt, uint32_t mplen, uint32_t mult, uint32_t ep, uint32_t devaddr) \"ITD @ 0x%08x: next 0x%08x - mplen %d, mult %d, ep %d, dev %d\"\n> -usb_ehci_sitd(uint32_t addr, uint32_t nxt, uint32_t active) \"ITD @ 0x%08x: next 0x%08x - active %d\"\n> +usb_ehci_qtd_ptrs(void *q, uint64_t addr, uint32_t nxt, uint32_t altnext) \"q %p - QTD @ 0x%\" PRIx64 \": next 0x%08x altnext 0x%08x\"\n> +usb_ehci_qtd_fields(uint64_t addr, int tbytes, int cpage, int cerr, int pid) \"QTD @ 0x%\" PRIx64 \" - tbytes %d, cpage %d, cerr %d, pid %d\"\n> +usb_ehci_qtd_bits(uint64_t addr, int ioc, int active, int halt, int babble, int xacterr) \"QTD @ 0x%\" PRIx64 \" - ioc %d, active %d, halt %d, babble %d, xacterr %d\"\n> +usb_ehci_itd(uint64_t addr, uint32_t nxt, uint32_t mplen, uint32_t mult, uint32_t ep, uint32_t devaddr) \"ITD @ 0x%\" PRIx64 \": next 0x%08x - mplen %d, mult %d, ep %d, dev %d\"\n> +usb_ehci_sitd(uint64_t addr, uint32_t nxt, uint32_t active) \"SITD @ 0x%\" PRIx64 \": next 0x%08x - active %d\"\n> usb_ehci_port_attach(uint32_t port, const char *owner, const char *device) \"attach port #%d, owner %s, device %s\"\n> usb_ehci_port_detach(uint32_t port, const char *owner) \"detach port #%d, owner %s\"\n> usb_ehci_port_reset(uint32_t port, int enable) \"reset port #%d - %d\"\n> @@ -104,15 +104,15 @@ usb_ehci_port_resume(uint32_t port) \"port #%d\"\n> usb_ehci_port_disable(uint32_t port) \"port #%d\"\n> usb_ehci_queue_action(void *q, const char *action) \"q %p: %s\"\n> usb_ehci_packet_action(void *q, void *p, const char *action) \"q %p p %p: %s\"\n> -usb_ehci_packet_submit(uint32_t qhaddr, uint32_t next, uint32_t qtdaddr, int pid, size_t len, int endp, int status, int actual_length) \"qh=0x%x, next=0x%x, qtd=0x%x, pid=0x%x, len=%zd, endp=0x%x, status=%d, actual_length=%d\"\n> +usb_ehci_packet_submit(uint64_t qhaddr, uint32_t next, uint64_t qtdaddr, int pid, size_t len, int endp, int status, int actual_length) \"qh=0x%\" PRIx64 \", next=0x%x, qtd=0x%\" PRIx64 \", pid=0x%x, len=%zd, endp=0x%x, status=%d, actual_length=%d\"\n> usb_ehci_irq(uint32_t level, uint32_t frindex, uint32_t sts, uint32_t mask) \"level %d, frindex 0x%04x, sts 0x%x, mask 0x%x\"\n> usb_ehci_guest_bug(const char *reason) \"%s\"\n> usb_ehci_doorbell_ring(void) \"\"\n> usb_ehci_doorbell_ack(void) \"\"\n> usb_ehci_dma_error(void) \"\"\n> -usb_ehci_execute_complete(uint32_t qhaddr, uint32_t next, uint32_t qtdaddr, int status, int actual_length) \"qhaddr=0x%x, next=0x%x, qtdaddr=0x%x, status=%d, actual_length=%d\"\n> -usb_ehci_fetchqh_reclaim_done(uint32_t qhaddr) \"QH 0x%08x H-bit set, reclamation status reset - done processing\"\n> -usb_ehci_fetchqh_dbg(uint32_t qhaddr, uint32_t h, uint32_t halt, uint32_t active, uint32_t next) \"QH 0x%08x (h 0x%x halt 0x%x active 0x%x) next 0x%08x\"\n> +usb_ehci_execute_complete(uint64_t qhaddr, uint32_t next, uint64_t qtdaddr, int status, int actual_length) \"qhaddr=0x%\" PRIx64 \", next=0x%x, qtdaddr=0x%\" PRIx64 \", status=%d, actual_length=%d\"\n> +usb_ehci_fetchqh_reclaim_done(uint64_t qhaddr) \"QH 0x%\" PRIx64 \" H-bit set, reclamation status reset - done processing\"\n> +usb_ehci_fetchqh_dbg(uint64_t qhaddr, uint32_t h, uint32_t halt, uint32_t active, uint32_t next) \"QH 0x%\" PRIx64 \" (h 0x%x halt 0x%x active 0x%x) next 0x%08x\"\n> usb_ehci_periodic_state_advance(uint32_t frame, uint32_t list, uint32_t entry) \"frame=%d, list=0x%x, entry=0x%x\"\n> usb_ehci_skipped_uframes(uint64_t skipped_uframes) \"skipped %\" PRIu64 \" uframes\"\n> usb_ehci_log(const char *msg) \"%s\"","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kaod.org header.i=@kaod.org header.a=rsa-sha256\n header.s=ovhmo393970-selector1 header.b=GzEgsBEN;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","garm.ovh; auth=pass\n (GARM-103G0055f68832e-19e0-4ba8-a30d-dff1762825e8,\n C846149266E0C9F4D826987B86006927C6E58490) smtp.auth=clg@kaod.org"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Z7r2MXLz1yD5\n\tfor ; Thu, 23 Apr 2026 21:47:04 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFsVB-0007Cf-ED; Thu, 23 Apr 2026 07:45:49 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wFsUt-0006qQ-7I\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 07:45:40 -0400","from smtpout4.mo533.mail-out.ovh.net ([46.105.32.238])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wFsUn-0006RW-NN\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 07:45:30 -0400","from director2.derp.mail-out.ovh.net\n (director2.derp.mail-out.ovh.net [79.137.60.36])\n by mo533.mail-out.ovh.net (Postfix) with ESMTPS id 4g1Z5r3B9cz60PL;\n Thu, 23 Apr 2026 11:45:20 +0000 (UTC)","from director2.derp.mail-out.ovh.net\n (director2.derp.mail-out.ovh.net. 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charset=utf-8","Content-Disposition":"inline","In-Reply-To":"<20260423051804.362095-9-jamin_lin@aspeedtech.com>","Received-SPF":"pass client-ip=170.10.133.124; envelope-from=peterx@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3681766,"web_url":"http://patchwork.ozlabs.org/comment/3681766/","msgid":"","list_archive_url":null,"date":"2026-04-24T03:53:32","subject":"RE: [PATCH v4 08/17] hw/usb/hcd-ehci: Change descriptor addresses to\n 64-bit with migration compatibility","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"content":"Hi Cédric\n\n> Subject: Re: [PATCH v4 08/17] hw/usb/hcd-ehci: Change descriptor addresses to\n> 64-bit with migration compatibility\n> \n> Hello Jamin,\n> \n> On 4/23/26 07:18, Jamin Lin wrote:\n> > Change internal EHCI descriptor addresses from uint32_t to uint64_t.\n> >\n> > The following fields are updated:\n> > - EHCIPacket::qtdaddr\n> > - EHCIQueue::{qhaddr, qtdaddr}\n> > - EHCIState::{a_fetch_addr, p_fetch_addr}\n> >\n> > Update get_dwords() and put_dwords() to take 64-bit addresses and\n> > propagate the type change through the descriptor traversal paths.\n> >\n> > Adjust NLPTR_GET() to operate on 64-bit values:\n> >\n> > #define NLPTR_GET(x) ((x) & ~0x1fULL)\n> >\n> > so that link pointer masking works correctly when descriptor addresses\n> > exceed 32-bit space. The previous mask (0xffffffe0) implicitly\n> > truncated addresses to 32 bits.\n> >\n> > This patch does not change the on-wire descriptor layout yet.\n> > It only removes the internal 32-bit address limit and prepares for\n> > later patches that will add full 64-bit QH/qTD/iTD/siTD support.\n> >\n> > Update the EHCI trace-events prototypes for QH, qTD, iTD, and siTD to\n> > use uint64_t for the address argument and print it with PRIx64. This\n> > ensures full 64-bit addresses are shown in trace output and improves\n> > debugging of queue heads and transfer descriptors.\n> >\n> > Migration compatibility:\n> >\n> > To preserve backward migration compatibility, keep the legacy 32-bit\n> > fetch address fields (a_fetch_addr_32, p_fetch_addr_32) alongside the\n> > new 64-bit fields.\n> >\n> > Migration format is selected using a machine compat property\n> > \"x-migrate-fetch-addr-64bit\":\n> >\n> > - Old machine types migrate 32-bit fetch addresses\n> > - New machine types migrate full 64-bit fetch addresses\n> >\n> > This is implemented using VMSTATE_UINT32_TEST() and\n> > VMSTATE_UINT64_TEST() so that only the appropriate format is migrated.\n> >\n> > In pre_save, the 32-bit shadow fields are populated when migrating to\n> > old machine types. In post_load, the 32-bit values are restored into\n> > the 64-bit fields when loading old migration streams.\n> >\n> > No functional change.\n> >\n> > Signed-off-by: Jamin Lin \n> > Reviewed-by: Philippe Mathieu-Daudé \n> \n> This patch was reworked significantly to handle migration and I don't think\n> Philippe's Reviewed-by stands anymore.\n> \n> Could you please explain how you tested ? QEMU command lines, which OS,\n> etc. ?\n> \n\nThe following are my test commands. I used the pc-q35-10.2 machine with the ubuntu-24.04-server-cloudimg-amd64 image.\n\nA. 10.2 forward to 11.0 + my patch\n\n1. QEMU version 10.2\n./build-10.2/qemu-system-x86_64 -M pc-q35-10.2 -m 2G -serial mon:stdio -nographic \\\n -drive file=ubuntu-24.04-server-cloudimg-amd64.img,format=qcow2 \\\n -drive file=user-data.img,format=raw \\\n -device usb-ehci,id=myehci0 \\\n -drive id=usbdisk,if=none,file=image0.ext4,format=raw \\\n -device usb-storage,bus=myehci0.0,id=mystorage,drive=usbdisk\n\n(qemu) migrate tcp:127.0.0.1:4444\n \n2. QEMU version 11.0 with my patches\n\n./build/qemu-system-x86_64 -M pc-q35-10.2 -m 2G -serial mon:stdio -nographic \\\n -drive file=../qemu-migration-test/ubuntu-24.04-server-cloudimg-amd64.img,format=qcow2 \\\n -drive file=../qemu-migration-test/user-data.img,format=raw \\\n -device usb-ehci,id=myehci0 \\\n -drive id=usbdisk,if=none,file=../qemu-migration-test/image0.ext4,format=raw \\\n -device usb-storage,bus=myehci0.0,id=mystorage,drive=usbdisk \\\n -incoming tcp:0:4444\n\nRun step 2 first. Then run step 1 and enter monitor mode to issue:\n(qemu) migrate tcp:127.0.0.1:4444\n\nA. 11.0 + my patch backward to 10.2\n\n1. QEMU version 10.2\n./build-10.2/qemu-system-x86_64 -M pc-q35-10.2 -m 2G -serial mon:stdio -nographic \\\n -drive file=ubuntu-24.04-server-cloudimg-amd64.img,format=qcow2 \\\n -drive file=user-data.img,format=raw \\\n -device usb-ehci,id=myehci0 \\\n -drive id=usbdisk,if=none,file=image0.ext4,format=raw \\\n -device usb-storage,bus=myehci0.0,id=mystorage,drive=usbdisk \\\n -incoming tcp:0:4444\n\n2. QEMU version 11.0 with my patches\n\n./build/qemu-system-x86_64 -M pc-q35-10.2 -m 2G -serial mon:stdio -nographic \\\n -drive file=../qemu-migration-test/ubuntu-24.04-server-cloudimg-amd64.img,format=qcow2 \\\n -drive file=../qemu-migration-test/user-data.img,format=raw \\\n -device usb-ehci,id=myehci0 \\\n -drive id=usbdisk,if=none,file=../qemu-migration-test/image0.ext4,format=raw \\\n -device usb-storage,bus=myehci0.0,id=mystorage,drive=usbdisk\n(qemu) migrate tcp:127.0.0.1:4444\n\nRun step 1 first. Then run step 2 and enter monitor mode to issue:\n(qemu) migrate tcp:127.0.0.1:4444\n\nThe following logs are shown on the server side:\n\nubuntu login: ubuntu\nPassword:\nWelcome to Ubuntu 24.04.4 LTS (GNU/Linux 6.8.0-106-generic x86_64)\n\nubuntu@ubuntu:~$ lsusb\nBus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub\nBus 001 Device 002: ID 46f4:0001 QEMU QEMU USB HARDDRIVE\nubuntu@ubuntu:~$ lspci\n00:03.0 USB controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 10)\nubuntu@ubuntu:~$ sudo mount /dev/sdc /mnt\nubuntu@ubuntu:~$ sha256sum /mnt/test_read_file\n4bbda032a9c844dd34d2dd8754f67a510b2109734b9e6ac367efb13b6144038f /mnt/test_read_file\n\nThanks,\nJamin\n\n> Thanks,\n> \n> C.\n> \n> > ---\n> > hw/usb/hcd-ehci.h | 17 +++++++----\n> > hw/core/machine.c | 2 ++\n> > hw/usb/hcd-ehci.c | 72\n> ++++++++++++++++++++++++++++++++-------------\n> > hw/usb/trace-events | 24 +++++++--------\n> > 4 files changed, 76 insertions(+), 39 deletions(-)\n> >\n> > diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index\n> > d038ee1e31..3acbddfc5c 100644\n> > --- a/hw/usb/hcd-ehci.h\n> > +++ b/hw/usb/hcd-ehci.h\n> > @@ -208,7 +208,7 @@ struct EHCIPacket {\n> > QTAILQ_ENTRY(EHCIPacket) next;\n> >\n> > EHCIqtd qtd; /* copy of current QTD (being worked on)\n> */\n> > - uint32_t qtdaddr; /* address QTD read from\n> */\n> > + uint64_t qtdaddr; /* address QTD read from\n> */\n> >\n> > USBPacket packet;\n> > QEMUSGList sgl;\n> > @@ -229,8 +229,8 @@ struct EHCIQueue {\n> > * when guest removes an entry (doorbell, handshake sequence)\n> > */\n> > EHCIqh qh; /* copy of current QH (being worked on)\n> */\n> > - uint32_t qhaddr; /* address QH read from\n> */\n> > - uint32_t qtdaddr; /* address QTD read from\n> */\n> > + uint64_t qhaddr; /* address QH read from\n> */\n> > + uint64_t qtdaddr; /* address QTD read from\n> */\n> > int last_pid; /* pid of last packet executed */\n> > USBDevice *dev;\n> > QTAILQ_HEAD(, EHCIPacket) packets; @@ -256,6 +256,7 @@ struct\n> > EHCIState {\n> >\n> > /* properties */\n> > uint32_t maxframes;\n> > + bool migrate_fetch_addr_64bit;\n> >\n> > /*\n> > * EHCI spec version 1.0 Section 2.3 @@ -294,8 +295,10 @@\n> > struct EHCIState {\n> > EHCIQueueHead pqueues;\n> >\n> > /* which address to look at next */\n> > - uint32_t a_fetch_addr;\n> > - uint32_t p_fetch_addr;\n> > + uint32_t a_fetch_addr_32;\n> > + uint32_t p_fetch_addr_32;\n> > + uint64_t a_fetch_addr;\n> > + uint64_t p_fetch_addr;\n> >\n> > USBPacket ipacket;\n> > QEMUSGList isgl;\n> > @@ -308,7 +311,9 @@ struct EHCIState {\n> > };\n> >\n> > #define DEFINE_EHCI_COMMON_PROPERTIES(_state) \\\n> > - DEFINE_PROP_UINT32(\"maxframes\", _state, ehci.maxframes, 128)\n> > + DEFINE_PROP_UINT32(\"maxframes\", _state, ehci.maxframes, 128), \\\n> > + DEFINE_PROP_BOOL(\"x-migrate-fetch-addr-64bit\", _state, \\\n> > + ehci.migrate_fetch_addr_64bit, true)\n> >\n> > extern const VMStateDescription vmstate_ehci;\n> >\n> > diff --git a/hw/core/machine.c b/hw/core/machine.c index\n> > 0aa77a57e9..e77400c7ab 100644\n> > --- a/hw/core/machine.c\n> > +++ b/hw/core/machine.c\n> > @@ -41,6 +41,8 @@\n> > GlobalProperty hw_compat_10_2[] = {\n> > { \"scsi-block\", \"migrate-pr\", \"off\" },\n> > { \"isa-cirrus-vga\", \"global-vmstate\", \"true\" },\n> > + { \"sysbus-ehci-usb\", \"x-migrate-fetch-addr-64bit\", \"off\" },\n> > + { \"pci-ehci-usb\", \"x-migrate-fetch-addr-64bit\", \"off\" },\n> > };\n> > const size_t hw_compat_10_2_len = G_N_ELEMENTS(hw_compat_10_2);\n> >\n> > diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index\n> > 28a60e4c1a..0c8bdb48ad 100644\n> > --- a/hw/usb/hcd-ehci.c\n> > +++ b/hw/usb/hcd-ehci.c\n> > @@ -72,7 +72,7 @@ typedef enum {\n> > } EHCI_STATES;\n> >\n> > /* macros for accessing fields within next link pointer entry */\n> > -#define NLPTR_GET(x) ((x) & 0xffffffe0)\n> > +#define NLPTR_GET(x) ((x) & ~0x1fULL)\n> > #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)\n> > #define NLPTR_TBIT(x) ((x) & 1) /* 1=invalid, 0=valid */\n> >\n> > @@ -287,7 +287,7 @@ static int ehci_get_state(EHCIState *s, int async)\n> > return async ? s->astate : s->pstate;\n> > }\n> >\n> > -static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t\n> > addr)\n> > +static void ehci_set_fetch_addr(EHCIState *s, int async, uint64_t\n> > +addr)\n> > {\n> > if (async) {\n> > s->a_fetch_addr = addr;\n> > @@ -296,7 +296,7 @@ static void ehci_set_fetch_addr(EHCIState *s, int\n> async, uint32_t addr)\n> > }\n> > }\n> >\n> > -static int ehci_get_fetch_addr(EHCIState *s, int async)\n> > +static uint64_t ehci_get_fetch_addr(EHCIState *s, int async)\n> > {\n> > return async ? s->a_fetch_addr : s->p_fetch_addr;\n> > }\n> > @@ -373,7 +373,7 @@ static inline bool ehci_periodic_enabled(EHCIState\n> *s)\n> > }\n> >\n> > /* Get an array of dwords from main memory */ -static inline int\n> > get_dwords(EHCIState *ehci, uint32_t addr,\n> > +static inline int get_dwords(EHCIState *ehci, uint64_t addr,\n> > uint32_t *buf, int num)\n> > {\n> > int i;\n> > @@ -395,7 +395,7 @@ static inline int get_dwords(EHCIState *ehci, uint32_t\n> addr,\n> > }\n> >\n> > /* Put an array of dwords in to main memory */ -static inline int\n> > put_dwords(EHCIState *ehci, uint32_t addr,\n> > +static inline int put_dwords(EHCIState *ehci, uint64_t addr,\n> > uint32_t *buf, int num)\n> > {\n> > int i;\n> > @@ -549,7 +549,7 @@ static void ehci_free_packet(EHCIPacket *p)\n> >\n> > /* queue management */\n> >\n> > -static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr,\n> > int async)\n> > +static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint64_t addr,\n> > +int async)\n> > {\n> > EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;\n> > EHCIQueue *q;\n> > @@ -622,7 +622,7 @@ static void ehci_free_queue(EHCIQueue *q, const\n> char *warn)\n> > g_free(q);\n> > }\n> >\n> > -static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t\n> > addr,\n> > +static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint64_t\n> > +addr,\n> > int async)\n> > {\n> > EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;\n> > @@ -1135,7 +1135,7 @@ static void ehci_flush_qh(EHCIQueue *q)\n> > {\n> > uint32_t *qh = (uint32_t *) &q->qh;\n> > uint32_t dwords = sizeof(EHCIqh) >> 2;\n> > - uint32_t addr = NLPTR_GET(q->qhaddr);\n> > + uint64_t addr = NLPTR_GET(q->qhaddr);\n> >\n> > put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);\n> > }\n> > @@ -1406,12 +1406,13 @@ static int ehci_execute(EHCIPacket *p, const\n> char *action)\n> > /* 4.7.2 */\n> > static int ehci_process_itd(EHCIState *ehci,\n> > EHCIitd *itd,\n> > - uint32_t addr)\n> > + uint64_t addr)\n> > {\n> > USBDevice *dev;\n> > USBEndpoint *ep;\n> > uint32_t i, len, pid, dir, devaddr, endp;\n> > - uint32_t pg, off, ptr1, ptr2, max, mult;\n> > + uint32_t pg, off, max, mult;\n> > + uint64_t ptr1, ptr2;\n> >\n> > ehci->periodic_sched_active = PERIODIC_ACTIVE;\n> >\n> > @@ -1528,7 +1529,7 @@ static int ehci_state_waitlisthead(EHCIState *ehci,\n> int async)\n> > EHCIqh qh;\n> > int i = 0;\n> > int again = 0;\n> > - uint32_t entry = ehci->asynclistaddr;\n> > + uint64_t entry = ehci->asynclistaddr;\n> >\n> > /* set reclamation flag at start event (4.8.6) */\n> > if (async) {\n> > @@ -1578,7 +1579,7 @@ out:\n> > static int ehci_state_fetchentry(EHCIState *ehci, int async)\n> > {\n> > int again = 0;\n> > - uint32_t entry = ehci_get_fetch_addr(ehci, async);\n> > + uint64_t entry = ehci_get_fetch_addr(ehci, async);\n> >\n> > if (NLPTR_TBIT(entry)) {\n> > ehci_set_state(ehci, async, EST_ACTIVE); @@ -1611,7 +1612,7\n> > @@ static int ehci_state_fetchentry(EHCIState *ehci, int async)\n> > default:\n> > /* TODO: handle FSTN type */\n> > qemu_log_mask(LOG_GUEST_ERROR,\n> > - \"FETCHENTRY: entry at 0x%x is of type %u \"\n> > + \"FETCHENTRY: entry at %\" PRIx64 \"is of type %\"\n> > + PRIu64\n> > \"which is not supported yet\\n\",\n> > entry, NLPTR_TYPE_GET(entry));\n> > return -1;\n> > @@ -1623,7 +1624,7 @@ out:\n> >\n> > static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)\n> > {\n> > - uint32_t entry;\n> > + uint64_t entry;\n> > EHCIQueue *q;\n> > EHCIqh qh;\n> >\n> > @@ -1712,7 +1713,7 @@ out:\n> >\n> > static int ehci_state_fetchitd(EHCIState *ehci, int async)\n> > {\n> > - uint32_t entry;\n> > + uint64_t entry;\n> > EHCIitd itd;\n> >\n> > assert(!async);\n> > @@ -1738,7 +1739,7 @@ static int ehci_state_fetchitd(EHCIState *ehci,\n> > int async)\n> >\n> > static int ehci_state_fetchsitd(EHCIState *ehci, int async)\n> > {\n> > - uint32_t entry;\n> > + uint64_t entry;\n> > EHCIsitd sitd;\n> >\n> > assert(!async);\n> > @@ -1802,7 +1803,7 @@ static int ehci_state_fetchqtd(EHCIQueue *q)\n> > EHCIqtd qtd;\n> > EHCIPacket *p;\n> > int again = 1;\n> > - uint32_t addr;\n> > + uint64_t addr;\n> >\n> > addr = NLPTR_GET(q->qtdaddr);\n> > if (get_dwords(q->ehci, addr + 8, &qtd.token, 1) < 0) {\n> > @@ -1885,7 +1886,7 @@ static int ehci_fill_queue(EHCIPacket *p)\n> > USBEndpoint *ep = p->packet.ep;\n> > EHCIQueue *q = p->queue;\n> > EHCIqtd qtd = p->qtd;\n> > - uint32_t qtdaddr;\n> > + uint64_t qtdaddr;\n> >\n> > for (;;) {\n> > if (NLPTR_TBIT(qtd.next) != 0) { @@ -2008,7 +2009,8 @@\n> > static int ehci_state_executing(EHCIQueue *q)\n> > static int ehci_state_writeback(EHCIQueue *q)\n> > {\n> > EHCIPacket *p = QTAILQ_FIRST(&q->packets);\n> > - uint32_t *qtd, addr;\n> > + uint32_t *qtd;\n> > + uint64_t addr;\n> > int again = 0;\n> >\n> > /* Write back the QTD from the QH area */ @@ -2414,6 +2416,18\n> > @@ static USBBusOps ehci_bus_ops_standalone = {\n> > .wakeup_endpoint = ehci_wakeup_endpoint,\n> > };\n> >\n> > +static bool ehci_fetch_addr_64_needed(void *opaque, int version_id) {\n> > + EHCIState *s = opaque;\n> > +\n> > + return s->migrate_fetch_addr_64bit; }\n> > +\n> > +static bool ehci_fetch_addr_32_needed(void *opaque, int version_id) {\n> > + return !ehci_fetch_addr_64_needed(opaque, version_id); }\n> > +\n> > static int usb_ehci_pre_save(void *opaque)\n> > {\n> > EHCIState *ehci = opaque;\n> > @@ -2424,6 +2438,11 @@ static int usb_ehci_pre_save(void *opaque)\n> > ehci->last_run_ns -= (ehci->frindex - new_frindex) *\n> UFRAME_TIMER_NS;\n> > ehci->frindex = new_frindex;\n> >\n> > + if (!ehci->migrate_fetch_addr_64bit) {\n> > + ehci->a_fetch_addr_32 = ehci->a_fetch_addr;\n> > + ehci->p_fetch_addr_32 = ehci->p_fetch_addr;\n> > + }\n> > +\n> > return 0;\n> > }\n> >\n> > @@ -2444,6 +2463,11 @@ static int usb_ehci_post_load(void *opaque, int\n> version_id)\n> > }\n> > }\n> >\n> > + if (!s->migrate_fetch_addr_64bit) {\n> > + s->a_fetch_addr = s->a_fetch_addr_32;\n> > + s->p_fetch_addr = s->p_fetch_addr_32;\n> > + }\n> > +\n> > return 0;\n> > }\n> >\n> > @@ -2504,8 +2528,14 @@ const VMStateDescription vmstate_ehci = {\n> > /* schedule state */\n> > VMSTATE_UINT32(astate, EHCIState),\n> > VMSTATE_UINT32(pstate, EHCIState),\n> > - VMSTATE_UINT32(a_fetch_addr, EHCIState),\n> > - VMSTATE_UINT32(p_fetch_addr, EHCIState),\n> > + VMSTATE_UINT32_TEST(a_fetch_addr_32, EHCIState,\n> > + ehci_fetch_addr_32_needed),\n> > + VMSTATE_UINT32_TEST(p_fetch_addr_32, EHCIState,\n> > + ehci_fetch_addr_32_needed),\n> > + VMSTATE_UINT64_TEST(a_fetch_addr, EHCIState,\n> > + ehci_fetch_addr_64_needed),\n> > + VMSTATE_UINT64_TEST(p_fetch_addr, EHCIState,\n> > + ehci_fetch_addr_64_needed),\n> > VMSTATE_END_OF_LIST()\n> > }\n> > };\n> > diff --git a/hw/usb/trace-events b/hw/usb/trace-events index\n> > 0d4318dcf1..8c90688bb3 100644\n> > --- a/hw/usb/trace-events\n> > +++ b/hw/usb/trace-events\n> > @@ -86,15 +86,15 @@ usb_ehci_portsc_write(uint32_t addr, uint32_t port,\n> uint32_t val) \"wr mmio 0x%04\n> > usb_ehci_portsc_change(uint32_t addr, uint32_t port, uint32_t new,\n> uint32_t old) \"ch mmio 0x%04x [port %d] = 0x%x (old: 0x%x)\"\n> > usb_ehci_usbsts(const char *sts, int state) \"usbsts %s %d\"\n> > usb_ehci_state(const char *schedule, const char *state) \"%s schedule %s\"\n> > -usb_ehci_qh_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t c_qtd,\n> uint32_t n_qtd, uint32_t a_qtd) \"q %p - QH @ 0x%08x: next 0x%08x qtds\n> 0x%08x,0x%08x,0x%08x\"\n> > -usb_ehci_qh_fields(uint32_t addr, int rl, int mplen, int eps, int ep, int\n> devaddr) \"QH @ 0x%08x - rl %d, mplen %d, eps %d, ep %d, dev %d\"\n> > -usb_ehci_qh_bits(uint32_t addr, int c, int h, int dtc, int i) \"QH @ 0x%08x - c\n> %d, h %d, dtc %d, i %d\"\n> > +usb_ehci_qh_ptrs(void *q, uint64_t addr, uint32_t nxt, uint32_t c_qtd,\n> uint32_t n_qtd, uint32_t a_qtd) \"q %p - QH @ 0x%\" PRIx64 \": next 0x%08x qtds\n> 0x%08x,0x%08x,0x%08x\"\n> > +usb_ehci_qh_fields(uint64_t addr, int rl, int mplen, int eps, int ep, int\n> devaddr) \"QH @ 0x%\" PRIx64 \" - rl %d, mplen %d, eps %d, ep %d, dev %d\"\n> > +usb_ehci_qh_bits(uint64_t addr, int c, int h, int dtc, int i) \"QH @ 0x%\"\n> PRIx64 \" - c %d, h %d, dtc %d, i %d\"\n> > usb_ehci_qh_tbytes(uint32_t tbytes) \"updating tbytes to %d\"\n> > -usb_ehci_qtd_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t altnext) \"q\n> %p - QTD @ 0x%08x: next 0x%08x altnext 0x%08x\"\n> > -usb_ehci_qtd_fields(uint32_t addr, int tbytes, int cpage, int cerr, int pid)\n> \"QTD @ 0x%08x - tbytes %d, cpage %d, cerr %d, pid %d\"\n> > -usb_ehci_qtd_bits(uint32_t addr, int ioc, int active, int halt, int babble, int\n> xacterr) \"QTD @ 0x%08x - ioc %d, active %d, halt %d, babble %d, xacterr %d\"\n> > -usb_ehci_itd(uint32_t addr, uint32_t nxt, uint32_t mplen, uint32_t mult,\n> uint32_t ep, uint32_t devaddr) \"ITD @ 0x%08x: next 0x%08x - mplen %d, mult\n> %d, ep %d, dev %d\"\n> > -usb_ehci_sitd(uint32_t addr, uint32_t nxt, uint32_t active) \"ITD @ 0x%08x:\n> next 0x%08x - active %d\"\n> > +usb_ehci_qtd_ptrs(void *q, uint64_t addr, uint32_t nxt, uint32_t altnext) \"q\n> %p - QTD @ 0x%\" PRIx64 \": next 0x%08x altnext 0x%08x\"\n> > +usb_ehci_qtd_fields(uint64_t addr, int tbytes, int cpage, int cerr, int pid)\n> \"QTD @ 0x%\" PRIx64 \" - tbytes %d, cpage %d, cerr %d, pid %d\"\n> > +usb_ehci_qtd_bits(uint64_t addr, int ioc, int active, int halt, int babble, int\n> xacterr) \"QTD @ 0x%\" PRIx64 \" - ioc %d, active %d, halt %d, babble %d, xacterr\n> %d\"\n> > +usb_ehci_itd(uint64_t addr, uint32_t nxt, uint32_t mplen, uint32_t mult,\n> uint32_t ep, uint32_t devaddr) \"ITD @ 0x%\" PRIx64 \": next 0x%08x - mplen %d,\n> mult %d, ep %d, dev %d\"\n> > +usb_ehci_sitd(uint64_t addr, uint32_t nxt, uint32_t active) \"SITD @ 0x%\"\n> PRIx64 \": next 0x%08x - active %d\"\n> > usb_ehci_port_attach(uint32_t port, const char *owner, const char\n> *device) \"attach port #%d, owner %s, device %s\"\n> > usb_ehci_port_detach(uint32_t port, const char *owner) \"detach port\n> #%d, owner %s\"\n> > usb_ehci_port_reset(uint32_t port, int enable) \"reset port #%d - %d\"\n> > @@ -104,15 +104,15 @@ usb_ehci_port_resume(uint32_t port) \"port #%d\"\n> > usb_ehci_port_disable(uint32_t port) \"port #%d\"\n> > usb_ehci_queue_action(void *q, const char *action) \"q %p: %s\"\n> > usb_ehci_packet_action(void *q, void *p, const char *action) \"q %p p %p:\n> %s\"\n> > -usb_ehci_packet_submit(uint32_t qhaddr, uint32_t next, uint32_t qtdaddr,\n> int pid, size_t len, int endp, int status, int actual_length) \"qh=0x%x, next=0x%x,\n> qtd=0x%x, pid=0x%x, len=%zd, endp=0x%x, status=%d, actual_length=%d\"\n> > +usb_ehci_packet_submit(uint64_t qhaddr, uint32_t next, uint64_t qtdaddr,\n> int pid, size_t len, int endp, int status, int actual_length) \"qh=0x%\" PRIx64 \",\n> next=0x%x, qtd=0x%\" PRIx64 \", pid=0x%x, len=%zd, endp=0x%x, status=%d,\n> actual_length=%d\"\n> > usb_ehci_irq(uint32_t level, uint32_t frindex, uint32_t sts, uint32_t mask)\n> \"level %d, frindex 0x%04x, sts 0x%x, mask 0x%x\"\n> > usb_ehci_guest_bug(const char *reason) \"%s\"\n> > usb_ehci_doorbell_ring(void) \"\"\n> > usb_ehci_doorbell_ack(void) \"\"\n> > usb_ehci_dma_error(void) \"\"\n> > -usb_ehci_execute_complete(uint32_t qhaddr, uint32_t next, uint32_t\n> qtdaddr, int status, int actual_length) \"qhaddr=0x%x, next=0x%x, qtdaddr=0x%x,\n> status=%d, actual_length=%d\"\n> > -usb_ehci_fetchqh_reclaim_done(uint32_t qhaddr) \"QH 0x%08x H-bit set,\n> reclamation status reset - done processing\"\n> > -usb_ehci_fetchqh_dbg(uint32_t qhaddr, uint32_t h, uint32_t halt, uint32_t\n> active, uint32_t next) \"QH 0x%08x (h 0x%x halt 0x%x active 0x%x) next\n> 0x%08x\"\n> > +usb_ehci_execute_complete(uint64_t qhaddr, uint32_t next, uint64_t\n> qtdaddr, int status, int actual_length) \"qhaddr=0x%\" PRIx64 \", next=0x%x,\n> qtdaddr=0x%\" PRIx64 \", status=%d, actual_length=%d\"\n> > +usb_ehci_fetchqh_reclaim_done(uint64_t qhaddr) \"QH 0x%\" PRIx64 \" H-bit\n> set, reclamation status reset - done processing\"\n> > +usb_ehci_fetchqh_dbg(uint64_t qhaddr, uint32_t h, uint32_t halt, uint32_t\n> active, uint32_t next) \"QH 0x%\" PRIx64 \" (h 0x%x halt 0x%x active 0x%x) next\n> 0x%08x\"\n> > usb_ehci_periodic_state_advance(uint32_t frame, uint32_t list, uint32_t\n> entry) \"frame=%d, list=0x%x, entry=0x%x\"\n> > usb_ehci_skipped_uframes(uint64_t skipped_uframes) \"skipped %\"\n> PRIu64 \" uframes\"\n> > usb_ehci_log(const char *msg) \"%s\"","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=TWqnR9lb;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=aspeedtech.com;"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No 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","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3681776,"web_url":"http://patchwork.ozlabs.org/comment/3681776/","msgid":"","list_archive_url":null,"date":"2026-04-24T06:03:38","subject":"RE: [PATCH v4 08/17] hw/usb/hcd-ehci: Change descriptor addresses to\n 64-bit with migration compatibility","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"content":"Hi Peter,\n\n> Subject: Re: [PATCH v4 08/17] hw/usb/hcd-ehci: Change descriptor addresses to\n> 64-bit with migration compatibility\n> \n> On Thu, Apr 23, 2026 at 05:18:15AM +0000, Jamin Lin wrote:\n> > diff --git a/hw/core/machine.c b/hw/core/machine.c index\n> > 0aa77a57e9..e77400c7ab 100644\n> > --- a/hw/core/machine.c\n> > +++ b/hw/core/machine.c\n> > @@ -41,6 +41,8 @@\n> > GlobalProperty hw_compat_10_2[] = {\n> > { \"scsi-block\", \"migrate-pr\", \"off\" },\n> > { \"isa-cirrus-vga\", \"global-vmstate\", \"true\" },\n> > + { \"sysbus-ehci-usb\", \"x-migrate-fetch-addr-64bit\", \"off\" },\n> > + { \"pci-ehci-usb\", \"x-migrate-fetch-addr-64bit\", \"off\" },\n> > };\n> \n> Sorry I forgot to comment here previously: we just released 11.0, I think it\n> means you want hw_compat_11_0[] now, otherwise someone using 11.0.0\n> released binary may hit issues migrating to some newer binaries before 11.1.\n> \nThanks for the review and suggestion.\nWill do\nJamin\n> --\n> Peter Xu","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=nxGH6cO+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender 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