[{"id":3681201,"web_url":"http://patchwork.ozlabs.org/comment/3681201/","msgid":"","list_archive_url":null,"date":"2026-04-22T23:00:15","subject":"Re: [PATCH v3 29/32] target/arm: implement global monitor events","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/22/26 22:52, Alex Bennée wrote:\n> Moving from Exclusive to Open Access should generate event stream\n> events. Technically a non-exclusive store to any address range covered\n> by the global monitor should also trigger such an event but we can\n> only detect that after the event by seeing if memory doesn't match\n> cpu_exclusive_val when processing the eventual store exclusive.\n> \n> The CLREX instruction has the same effect as do other operations\n> clearing the exclusive state (such as eret).\n> \n> We special case STLR/STL (Store Release) instructions to generate\n> events because their use is a suggested pattern for clearing locks\n> that might be sleeping. We only trigger the event if we detect an\n> exclusive instruction is running.\n> \n> Signed-off-by: Alex Bennée \n> \n> ---\n> v2\n> - add gen_global_event_reg() and use that\n> - add handling for STL/STLR\n> ---\n> target/arm/internals.h | 1 +\n> target/arm/tcg/translate.h | 14 ++++++++++++++\n> target/arm/tcg/translate-a64.c | 23 +++++++++++++++++++++++\n> target/arm/tcg/translate.c | 20 ++++++++++++++++++++\n> 4 files changed, 58 insertions(+)\n> \n> diff --git a/target/arm/internals.h b/target/arm/internals.h\n> index 089f679ac0a..7045b4a56bd 100644\n> --- a/target/arm/internals.h\n> +++ b/target/arm/internals.h\n> @@ -709,6 +709,7 @@ static inline void arm_broadcast_event(void)\n> static inline void arm_clear_exclusive(CPUARMState *env)\n> {\n> env->exclusive_addr = -1;\n> + arm_broadcast_event();\n> }\n\nAn out-of-line arm_broadcast_event suggests an out of line arm_clear_exclusive too.\n\n> @@ -3544,6 +3553,7 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n> TCGv_i64 clean_addr;\n> MemOp memop;\n> bool iss_sf = ldst_iss_sf(a->sz, false, false);\n> + TCGLabel *skip_monitor_event = gen_new_label();\n> \n> /*\n> * StoreLORelease is the same as Store-Release for QEMU, but\n> @@ -3562,6 +3572,19 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n> true, a->rn != 31, memop);\n> do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt,\n> iss_sf, a->lasr);\n> +\n> + /*\n> + * We don't fully model the global monitor as it would be very\n> + * expensive for every memory access. However in the Arm ARM \"Use\n> + * of Wait for Event (WFE) and Send Event (SEV) with lock\" it does\n> + * give the example of using STLR to clear a lock. So if a lock is\n> + * active trigger the global event register so we don't deadlock\n> + * while sleeping.\n> + */\n> + tcg_gen_brcondi_i64(TCG_COND_EQ, cpu_exclusive_addr, -1, skip_monitor_event);\n> + gen_global_event_reg();\n> + gen_set_label(skip_monitor_event);\n> +\n> return true;\n> }\n> \n\nUm, no. Just because STLR is used in the example, *any* change to the memory region must \nraise the event. There's nothing special about STLR vs STL vs STB etc.\n\nThe only thing I can think that would handle this is to set up a watchpoint in WFE before \ngoing to sleep, then wake on the watchpoint trigger. Disabling the watchpoint on any \nother wakeup could be annoying.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=A7yd1vRk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1F7x3Yn8z1yD5\n\tfor ; Thu, 23 Apr 2026 09:01:01 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFgYW-0002ai-FN; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::435;\n envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3681415,"web_url":"http://patchwork.ozlabs.org/comment/3681415/","msgid":"<87se8lx4jq.fsf@draig.linaro.org>","list_archive_url":null,"date":"2026-04-23T12:08:25","subject":"Re: [PATCH v3 29/32] target/arm: implement global monitor events","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Richard Henderson writes:\n\n> On 4/22/26 22:52, Alex Bennée wrote:\n>> Moving from Exclusive to Open Access should generate event stream\n>> events. Technically a non-exclusive store to any address range covered\n>> by the global monitor should also trigger such an event but we can\n>> only detect that after the event by seeing if memory doesn't match\n>> cpu_exclusive_val when processing the eventual store exclusive.\n>> The CLREX instruction has the same effect as do other operations\n>> clearing the exclusive state (such as eret).\n>> We special case STLR/STL (Store Release) instructions to generate\n>> events because their use is a suggested pattern for clearing locks\n>> that might be sleeping. We only trigger the event if we detect an\n>> exclusive instruction is running.\n>> Signed-off-by: Alex Bennée \n>> ---\n>> v2\n>> - add gen_global_event_reg() and use that\n>> - add handling for STL/STLR\n>> ---\n>> target/arm/internals.h | 1 +\n>> target/arm/tcg/translate.h | 14 ++++++++++++++\n>> target/arm/tcg/translate-a64.c | 23 +++++++++++++++++++++++\n>> target/arm/tcg/translate.c | 20 ++++++++++++++++++++\n>> 4 files changed, 58 insertions(+)\n>> diff --git a/target/arm/internals.h b/target/arm/internals.h\n>> index 089f679ac0a..7045b4a56bd 100644\n>> --- a/target/arm/internals.h\n>> +++ b/target/arm/internals.h\n>> @@ -709,6 +709,7 @@ static inline void arm_broadcast_event(void)\n>> static inline void arm_clear_exclusive(CPUARMState *env)\n>> {\n>> env->exclusive_addr = -1;\n>> + arm_broadcast_event();\n>> }\n>\n> An out-of-line arm_broadcast_event suggests an out of line arm_clear_exclusive too.\n>\n>> @@ -3544,6 +3553,7 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n>> TCGv_i64 clean_addr;\n>> MemOp memop;\n>> bool iss_sf = ldst_iss_sf(a->sz, false, false);\n>> + TCGLabel *skip_monitor_event = gen_new_label();\n>> /*\n>> * StoreLORelease is the same as Store-Release for QEMU, but\n>> @@ -3562,6 +3572,19 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n>> true, a->rn != 31, memop);\n>> do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt,\n>> iss_sf, a->lasr);\n>> +\n>> + /*\n>> + * We don't fully model the global monitor as it would be very\n>> + * expensive for every memory access. However in the Arm ARM \"Use\n>> + * of Wait for Event (WFE) and Send Event (SEV) with lock\" it does\n>> + * give the example of using STLR to clear a lock. So if a lock is\n>> + * active trigger the global event register so we don't deadlock\n>> + * while sleeping.\n>> + */\n>> + tcg_gen_brcondi_i64(TCG_COND_EQ, cpu_exclusive_addr, -1, skip_monitor_event);\n>> + gen_global_event_reg();\n>> + gen_set_label(skip_monitor_event);\n>> +\n>> return true;\n>> }\n>> \n>\n> Um, no. Just because STLR is used in the example, *any* change to the\n> memory region must raise the event. There's nothing special about\n> STLR vs STL vs STB etc.\n\nI think in the context of locks the release is important. But yes I\nagree this isn't covering all the global monitor cases.\n\n> The only thing I can think that would handle this is to set up a\n> watchpoint in WFE before going to sleep, then wake on the watchpoint\n> trigger. Disabling the watchpoint on any other wakeup could be\n> annoying.\n\nThe global monitor and the event stream are different things though. So\nif we are committing to fully modelling the monitor (which would also\nsolve the ABA issue) it couldn't just be active while doing WFEs.\n\nWe could generate a postscript for every store which might be cheaper\nthan slow-pathing a whole page for the global monitor. If we supported\nsub-pages maybe slow-pathing a cache-lines worth of address space makes\nmore sense.\n\nAnother option would be exposing a exclusive address mask as a dedicated\nregister to the backend and making the check part of the softmmu\ngenerated code?\n\nI guess we could put the monitor active state in tb_flags to avoid the\ncost of code generation when no one uses ldstexcl because they have\naccess to far atomics instead?\n\n>\n>\n> r~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=OivWCho1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1ZdQ4Rfzz1yCv\n\tfor ; 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emacs 30.1","Date":"Thu, 23 Apr 2026 13:08:25 +0100","Message-ID":"<87se8lx4jq.fsf@draig.linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::331;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3681451,"web_url":"http://patchwork.ozlabs.org/comment/3681451/","msgid":"<8c223aa8-f8a2-485a-b9db-56b022d86cc2@linaro.org>","list_archive_url":null,"date":"2026-04-23T12:59:58","subject":"Re: [PATCH v3 29/32] target/arm: implement global monitor events","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/23/26 22:08, Alex Bennée wrote:\n>> Um, no. Just because STLR is used in the example, *any* change to the\n>> memory region must raise the event. There's nothing special about\n>> STLR vs STL vs STB etc.\n> \n> I think in the context of locks the release is important.\n\nNo, it's not. Notice the aa32 example uses STR.\n\n\n>> The only thing I can think that would handle this is to set up a\n>> watchpoint in WFE before going to sleep, then wake on the watchpoint\n>> trigger. Disabling the watchpoint on any other wakeup could be\n>> annoying.\n> \n> The global monitor and the event stream are different things though. So\n> if we are committing to fully modelling the monitor (which would also\n> solve the ABA issue) it couldn't just be active while doing WFEs.\n\nI didn't suggest fully modeling the monitor.\n\n\n> We could generate a postscript for every store which might be cheaper\n> than slow-pathing a whole page for the global monitor. If we supported\n> sub-pages maybe slow-pathing a cache-lines worth of address space makes\n> more sense.\n\nNot a chance.\n\n> Another option would be exposing a exclusive address mask as a dedicated\n> register to the backend and making the check part of the softmmu\n> generated code?\n\nI'm not sure I understand this suggestion.\n\n> I guess we could put the monitor active state in tb_flags to avoid the\n> cost of code generation when no one uses ldstexcl because they have\n> access to far atomics instead?\n\nMonitor active state is a global thing. I really don't see how you're going to \nsynchronize selection of that tb state globally.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=my++W8L1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1bn80qzlz1yD5\n\tfor ; Thu, 23 Apr 2026 23:00:58 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFtfE-000542-SZ; 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