[{"id":3680605,"web_url":"http://patchwork.ozlabs.org/comment/3680605/","msgid":"","list_archive_url":null,"date":"2026-04-22T12:47:57","subject":"Re: [Intel-wired-lan] [PATCH iwl-net 1/2] ice: ptp: serialize E825\n PHY timer start with PTP lock","submitter":{"id":75597,"url":"http://patchwork.ozlabs.org/api/people/75597/","name":"Loktionov, Aleksandr","email":"aleksandr.loktionov@intel.com"},"content":"> -----Original Message-----\n> From: Intel-wired-lan On Behalf\n> Of Grzegorz Nitka\n> Sent: Wednesday, April 22, 2026 2:32 PM\n> To: intel-wired-lan@lists.osuosl.org\n> Cc: netdev@vger.kernel.org; Kubalewski, Arkadiusz\n> ; Nguyen, Anthony L\n> ; Kitszel, Przemyslaw\n> \n> Subject: [Intel-wired-lan] [PATCH iwl-net 1/2] ice: ptp: serialize\n> E825 PHY timer start with PTP lock\n> \n> ice_start_phy_timer_eth56g() programs TIMETUS registers and issues\n> INIT_INCVAL without holding the global PTP semaphore.\n> \n> This allows concurrent PTP command paths to interleave with PHY timer\n> start, which can make the sequence fail and leave timer initialization\n> inconsistent.\n> \n> Take the PTP lock around TIMETUS registers programming and INIT_INCVAL\n> command execution, and make sure the lock is released on all error\n> paths.\n> \n> Keep the subsequent sync step outside of this critical section, since\n> ice_sync_phy_timer_eth56g() takes the same semaphore internally.\n> \n> Fixes: 7cab44f1c35f (\"ice: Introduce ETH56G PHY model for E825C\n> products\")\n> Reviewed-by: Arkadiusz Kubalewski \n> Signed-off-by: Grzegorz Nitka \n\nI recommend to add Cc: stable@vger.kernel.org\n\nReviewed-by: Aleksandr Loktionov \n\n> ---\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 15 +++++++++++++--\n> 1 file changed, 13 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> index 672218e5d1f9..8bb94e785f2a 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> @@ -2141,16 +2141,23 @@ int ice_start_phy_timer_eth56g(struct ice_hw\n> *hw, u8 port)\n> \t}\n> \tincval = (u64)hi << 32 | lo;\n> \n> +\tif (!ice_ptp_lock(hw)) {\n> +\t\tdev_err(ice_hw_to_dev(hw), \"Failed to acquire PTP\n> semaphore\\n\");\n> +\t\treturn -EBUSY;\n> +\t}\n> +\n> \terr = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,\n> incval);\n> \tif (err)\n> -\t\treturn err;\n> +\t\tgoto err_ptp_unlock;\n> \n> \terr = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);\n> \tif (err)\n> -\t\treturn err;\n> +\t\tgoto err_ptp_unlock;\n> \n> \tice_ptp_exec_tmr_cmd(hw);\n> \n> +\tice_ptp_unlock(hw);\n> +\n> \terr = ice_sync_phy_timer_eth56g(hw, port);\n> \tif (err)\n> \t\treturn err;\n> @@ -2166,6 +2173,10 @@ int ice_start_phy_timer_eth56g(struct ice_hw\n> *hw, u8 port)\n> \tice_debug(hw, ICE_DBG_PTP, \"Enabled clock on PHY port %u\\n\",\n> port);\n> \n> \treturn 0;\n> +\n> +err_ptp_unlock:\n> +\tice_ptp_unlock(hw);\n> +\treturn err;\n> }\n> \n> /**\n> --\n> 2.39.3","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=dnq08Ybu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; 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