[{"id":3681600,"web_url":"http://patchwork.ozlabs.org/comment/3681600/","msgid":"<02211194-CC8D-496B-A701-41453A01FB48@linux.ibm.com>","date":"2026-04-23T17:50:42","subject":"Re: [PATCH] powerpc/perf: Update check for PERF_SAMPLE_DATA_SRC\n marked events","submitter":{"id":90290,"url":"http://patchwork.ozlabs.org/api/people/90290/","name":"Athira Rajeev","email":"atrajeev@linux.ibm.com"},"content":"> On 21 Apr 2026, at 8:36 PM, Shivani Nittor wrote:\n> \n> The core-book3s PMU sampling code validates the SIER TYPE field\n> when PERF_SAMPLE_DATA_SRC is requested. The SIER TYPE field\n> indicates the instruction type and is only valid for\n> random sampling (marked events). To handle cases observed where\n> SIER TYPE could be zero even for marked events,validation was\n> added to drop such samples and increment event->lost_samples.\n> \n> However, this validation was applied to all samples,\n> including continuous sampling. In continuous sampling mode,\n> the PMU does not set the SIER TYPE field, so it remains zero.\n> As a result, valid continuous samples were incorrectly\n> treated as invalid and dropped. Fixed this by gating the\n> SIER TYPE validation with mark_event, so the check runs only\n> for marked (random) events. Continuous samples now skip this\n> check and are recorded normally in the final data recording path.\n> \n> Fixes: 2ffb26afa642 (\"arch/powerpc/perf: Check the instruction type before creating sample with perf_mem_data_src\")\n> Signed-off-by: Shivani Nittor \n\nThe changes looks good to me.\n\nReviewed-by : Athira Rajeev >\n\nThanks\nAthira\n> ---\n> \n> arch/powerpc/perf/core-book3s.c | 5 +++--\n> 1 file changed, 3 insertions(+), 2 deletions(-)\n> \n> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c\n> index 8b0081441f85..2e6adf5b95c4 100644\n> --- a/arch/powerpc/perf/core-book3s.c\n> +++ b/arch/powerpc/perf/core-book3s.c\n> @@ -2242,6 +2242,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,\n> const u64 last_period = event->hw.last_period;\n> s64 prev, delta, left;\n> int record = 0;\n> + int mark_event = regs->dsisr & MMCRA_SAMPLE_ENABLE;\n> \n> if (event->hw.state & PERF_HES_STOPPED) {\n> write_pmc(event->hw.idx, 0);\n> @@ -2304,9 +2305,9 @@ static void record_and_restart(struct perf_event *event, unsigned long val,\n> * In ISA v3.0 and before values \"0\" and \"7\" are considered reserved.\n> * In ISA v3.1, value \"7\" has been used to indicate \"larx/stcx\".\n> * Drop the sample if \"type\" has reserved values for this field with a\n> - * ISA version check.\n> + * ISA version check for marked events.\n> */\n> - if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&\n> + if (mark_event && event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&\n> ppmu->get_mem_data_src) {\n> val = (regs->dar & SIER_TYPE_MASK) >> SIER_TYPE_SHIFT;\n> if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31))) {\n> -- \n> 2.47.3\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=elwx7Z+U;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; 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