[{"id":3680159,"web_url":"http://patchwork.ozlabs.org/comment/3680159/","msgid":"","list_archive_url":null,"date":"2026-04-22T00:59:41","subject":"Re: [PATCH 4/8] iommu/msm: Look up masters per IOMMU instance","submitter":{"id":90483,"url":"http://patchwork.ozlabs.org/api/people/90483/","name":"Dmitry Baryshkov","email":"dmitry.baryshkov@oss.qualcomm.com"},"content":"On Tue, Apr 21, 2026 at 11:45:10AM +0200, Alexandre MINETTE via B4 Relay wrote:\n> From: Alexandre MINETTE \n> \n> MSM IOMMU stores context descriptors on each IOMMU instance. Looking up\n> the descriptor through dev_iommu_priv_get() is not sufficient because a\n> device can reference multiple IOMMU provider nodes.\n> \n> Look up the master from the target IOMMU ctx_list instead, and use the\n> same helper when probing and attaching devices. This avoids dereferencing\n> a NULL master when an IOMMU already has context entries for another\n> device, and keeps separate context descriptors for separate IOMMU\n> instances.\n> \n> This is required to boot APQ8064 boards using multiple IOMMU contexts.\n\nWhich cores / devices? Could you please add a (trimmed) backtrace? Also\na Fixes tag would be nice.\n\n> \n> Signed-off-by: Alexandre MINETTE \n> ---\n> drivers/iommu/msm_iommu.c | 28 ++++++++++++++++------------\n> 1 file changed, 16 insertions(+), 12 deletions(-)\n> \n> diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c\n> index 0ad5ff431d5b..9c03878d0d2c 100644\n> --- a/drivers/iommu/msm_iommu.c\n> +++ b/drivers/iommu/msm_iommu.c\n> @@ -357,17 +357,25 @@ static int msm_iommu_domain_config(struct msm_priv *priv)\n> \treturn 0;\n> }\n> \n> +static struct msm_iommu_ctx_dev *find_iommu_master(struct msm_iommu_dev *iommu,\n> +\t\t\t\t\t\t struct device *dev)\n> +{\n> +\tstruct msm_iommu_ctx_dev *master;\n> +\n> +\tlist_for_each_entry(master, &iommu->ctx_list, list)\n> +\t\tif (master->of_node == dev->of_node)\n> +\t\t\treturn master;\n> +\n> +\treturn NULL;\n> +}\n> +\n> /* Must be called under msm_iommu_lock */\n> static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev)\n> {\n> \tstruct msm_iommu_dev *iommu, *ret = NULL;\n> -\tstruct msm_iommu_ctx_dev *master;\n> \n> \tlist_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {\n> -\t\tmaster = list_first_entry(&iommu->ctx_list,\n> -\t\t\t\t\t struct msm_iommu_ctx_dev,\n> -\t\t\t\t\t list);\n> -\t\tif (master->of_node == dev->of_node) {\n> +\t\tif (find_iommu_master(iommu, dev)) {\n> \t\t\tret = iommu;\n> \t\t\tbreak;\n> \t\t}\n> @@ -405,10 +413,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev,\n> \n> \tspin_lock_irqsave(&msm_iommu_lock, flags);\n> \tlist_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {\n> -\t\tmaster = list_first_entry(&iommu->ctx_list,\n> -\t\t\t\t\t struct msm_iommu_ctx_dev,\n> -\t\t\t\t\t list);\n> -\t\tif (master->of_node == dev->of_node) {\n> +\t\tif (find_iommu_master(iommu, dev)) {\n> \t\t\tret = __enable_clocks(iommu);\n> \t\t\tif (ret)\n> \t\t\t\tgoto fail;\n> @@ -601,10 +606,10 @@ static int insert_iommu_master(struct device *dev,\n> \t\t\t\tstruct msm_iommu_dev **iommu,\n> \t\t\t\tconst struct of_phandle_args *spec)\n> {\n> -\tstruct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev);\n> +\tstruct msm_iommu_ctx_dev *master = find_iommu_master(*iommu, dev);\n> \tint sid;\n> \n> -\tif (list_empty(&(*iommu)->ctx_list)) {\n> +\tif (!master) {\n> \t\tmaster = kzalloc_obj(*master, GFP_ATOMIC);\n> \t\tif (!master) {\n> \t\t\tdev_err(dev, \"Failed to allocate iommu_master\\n\");\n> @@ -612,7 +617,6 @@ static int insert_iommu_master(struct device *dev,\n> \t\t}\n> \t\tmaster->of_node = dev->of_node;\n> \t\tlist_add(&master->list, &(*iommu)->ctx_list);\n> -\t\tdev_iommu_priv_set(dev, master);\n> \t}\n> \n> \tfor (sid = 0; sid < master->num_mids; sid++)\n> \n> -- \n> 2.43.0\n> \n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=mHyuQXwW;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=i3VqAByc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35319-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"mHyuQXwW\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"i3VqAByc\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.168.131","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0gql2cfNz1yGs\n\tfor ; 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