[{"id":3680145,"web_url":"http://patchwork.ozlabs.org/comment/3680145/","msgid":"","list_archive_url":null,"date":"2026-04-22T00:02:16","subject":"Re: [PATCH v3 1/2] target/riscv: Update MISA.C for Zc* extensions","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 6:01 PM wrote:\n>\n> From: Frank Chang \n>\n> MISA.C is set if the following extensions are selected:\n> * Zca and not F.\n> * Zca, Zcf and F (but not D) is specified (RV32 only).\n> * Zca, Zcf and Zcd if D is specified (RV32 only).\n> * Zca, Zcd if D is specified (RV64 only).\n>\n> Therefore, we need to set MISA.C according to the rules for Zc*\n> extensions.\n>\n> Signed-off-by: Frank Chang \n> Reviewed-by: Max Chou \n> ---\n> target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++++++++++++++++\n> 1 file changed, 32 insertions(+)\n>\n> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\n> index f3f78088956..0f68560bac1 100644\n> --- a/target/riscv/tcg/tcg-cpu.c\n> +++ b/target/riscv/tcg/tcg-cpu.c\n> @@ -1163,6 +1163,37 @@ static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)\n> }\n> }\n>\n> +/*\n> + * MISA.C is set if the following extensions are selected:\n> + * - Zca and not F.\n> + * - Zca, Zcf and F (but not D) is specified on RV32.\n> + * - Zca, Zcf and Zcd if D is specified on RV32.\n> + * - Zca, Zcd if D is specified on RV64.\n> + */\n> +static void riscv_cpu_update_misa_c(RISCVCPU *cpu)\n> +{\n> + CPURISCVState *env = &cpu->env;\n> +\n> + if (cpu->cfg.ext_zca && !riscv_has_ext(env, RVF)) {\n> + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC);\n> + return;\n> + }\n> +\n> + if (riscv_cpu_mxl(env) == MXL_RV32 &&\n> + cpu->cfg.ext_zca && cpu->cfg.ext_zcf &&\n> + (riscv_has_ext(env, RVD) ? cpu->cfg.ext_zcd :\n> + riscv_has_ext(env, RVF))) {\n> + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC);\n> + return;\n> + }\n> +\n> + if (riscv_cpu_mxl(env) == MXL_RV64 &&\n> + cpu->cfg.ext_zca && cpu->cfg.ext_zcd) {\n> + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC);\n> + return;\n> + }\n> +}\n> +\n> void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n> {\n> CPURISCVState *env = &cpu->env;\n> @@ -1170,6 +1201,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n>\n> riscv_cpu_init_implied_exts_rules();\n> riscv_cpu_enable_implied_rules(cpu);\n> + riscv_cpu_update_misa_c(cpu);\n\nWhat happens if a user has disabled C?\n\nAlistair\n\n>\n> riscv_cpu_validate_misa_priv(env, &local_err);\n> if (local_err != NULL) {\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=rEYJBzR8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF 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+1000","X-Gm-Features":"AQROBzBR2RFrYw_T6oGvl6s6mSLSFhmRhMkoWuHVc1cDiemiXDiWixqdb_EALoo","Message-ID":"\n ","Subject":"Re: [PATCH v3 1/2] target/riscv: Update MISA.C for Zc* extensions","To":"frank.chang@sifive.com","Cc":"qemu-devel@nongnu.org, Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n \"open list:RISC-V TCG CPUs\" ,\n Max Chou ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::62f;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x62f.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3681772,"web_url":"http://patchwork.ozlabs.org/comment/3681772/","msgid":"","list_archive_url":null,"date":"2026-04-24T05:07:38","subject":"Re: [PATCH v3 1/2] target/riscv: Update MISA.C for Zc* extensions","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/","name":"Frank Chang","email":"frank.chang@sifive.com"},"content":"On Wed, Apr 22, 2026 at 8:02 AM Alistair Francis \nwrote:\n\n> On Tue, Apr 21, 2026 at 6:01 PM wrote:\n> >\n> > From: Frank Chang \n> >\n> > MISA.C is set if the following extensions are selected:\n> > * Zca and not F.\n> > * Zca, Zcf and F (but not D) is specified (RV32 only).\n> > * Zca, Zcf and Zcd if D is specified (RV32 only).\n> > * Zca, Zcd if D is specified (RV64 only).\n> >\n> > Therefore, we need to set MISA.C according to the rules for Zc*\n> > extensions.\n> >\n> > Signed-off-by: Frank Chang \n> > Reviewed-by: Max Chou \n> > ---\n> > target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++++++++++++++++\n> > 1 file changed, 32 insertions(+)\n> >\n> > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\n> > index f3f78088956..0f68560bac1 100644\n> > --- a/target/riscv/tcg/tcg-cpu.c\n> > +++ b/target/riscv/tcg/tcg-cpu.c\n> > @@ -1163,6 +1163,37 @@ static void\n> riscv_cpu_enable_implied_rules(RISCVCPU *cpu)\n> > }\n> > }\n> >\n> > +/*\n> > + * MISA.C is set if the following extensions are selected:\n> > + * - Zca and not F.\n> > + * - Zca, Zcf and F (but not D) is specified on RV32.\n> > + * - Zca, Zcf and Zcd if D is specified on RV32.\n> > + * - Zca, Zcd if D is specified on RV64.\n> > + */\n> > +static void riscv_cpu_update_misa_c(RISCVCPU *cpu)\n> > +{\n> > + CPURISCVState *env = &cpu->env;\n> > +\n> > + if (cpu->cfg.ext_zca && !riscv_has_ext(env, RVF)) {\n> > + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC);\n> > + return;\n> > + }\n> > +\n> > + if (riscv_cpu_mxl(env) == MXL_RV32 &&\n> > + cpu->cfg.ext_zca && cpu->cfg.ext_zcf &&\n> > + (riscv_has_ext(env, RVD) ? cpu->cfg.ext_zcd :\n> > + riscv_has_ext(env, RVF))) {\n> > + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC);\n> > + return;\n> > + }\n> > +\n> > + if (riscv_cpu_mxl(env) == MXL_RV64 &&\n> > + cpu->cfg.ext_zca && cpu->cfg.ext_zcd) {\n> > + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC);\n> > + return;\n> > + }\n> > +}\n> > +\n> > void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n> > {\n> > CPURISCVState *env = &cpu->env;\n> > @@ -1170,6 +1201,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU\n> *cpu, Error **errp)\n> >\n> > riscv_cpu_init_implied_exts_rules();\n> > riscv_cpu_enable_implied_rules(cpu);\n> > + riscv_cpu_update_misa_c(cpu);\n>\n> What happens if a user has disabled C?\n>\n> Alistair\n>\n\nHi Alistair,\n\nI've added the warning message when user disables RVC explicitly,\nbut RVC is mandated by Zca/Zcf/Zcd extensions in the next patchset:\nhttps://lore.kernel.org/qemu-devel/20260424050509.3935180-1-frank.chang@sifive.com/\n\nRegards,\nFrank Chang\n\n\n>\n> >\n> > riscv_cpu_validate_misa_priv(env, &local_err);\n> > if (local_err != NULL) {\n> > --\n> > 2.43.0\n> >\n> >\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=b/9Wt3jW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n 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