[{"id":3680144,"web_url":"http://patchwork.ozlabs.org/comment/3680144/","msgid":"","list_archive_url":null,"date":"2026-04-22T00:01:38","subject":"Re: [PATCH v3 2/2] target/riscv: Update MISA.X for non-standard\n extensions","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 6:00 PM wrote:\n>\n> From: Frank Chang \n>\n> MISA.X is set if there are any non-standard extensions.\n> We should set MISA.X when any of the vendor extensions is enabled.\n>\n> Signed-off-by: Frank Chang \n> Reviewed-by: Max Chou \n> Reviewed-by: Daniel Henrique Barboza \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> target/riscv/cpu.h | 1 +\n> target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++\n> 2 files changed, 16 insertions(+)\n>\n> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\n> index 4c0676ed53b..175e877f90a 100644\n> --- a/target/riscv/cpu.h\n> +++ b/target/riscv/cpu.h\n> @@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;\n> #define RVH RV('H')\n> #define RVG RV('G')\n> #define RVB RV('B')\n> +#define RVX RV('X')\n>\n> extern const uint32_t misa_bits[];\n> const char *riscv_get_misa_ext_name(uint32_t bit);\n> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\n> index 0f68560bac1..44d948b5dca 100644\n> --- a/target/riscv/tcg/tcg-cpu.c\n> +++ b/target/riscv/tcg/tcg-cpu.c\n> @@ -1194,6 +1194,20 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu)\n> }\n> }\n>\n> +/* MISA.X is set when any of the non-standard extensions is enabled. */\n> +static void riscv_cpu_update_misa_x(RISCVCPU *cpu)\n> +{\n> + CPURISCVState *env = &cpu->env;\n> + const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;\n> +\n> + for (int i = 0; arr[i].name != NULL; i++) {\n> + if (isa_ext_is_enabled(cpu, arr[i].offset)) {\n> + riscv_cpu_set_misa_ext(env, env->misa_ext | RVX);\n> + break;\n> + }\n> + }\n> +}\n> +\n> void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n> {\n> CPURISCVState *env = &cpu->env;\n> @@ -1202,6 +1216,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n> riscv_cpu_init_implied_exts_rules();\n> riscv_cpu_enable_implied_rules(cpu);\n> riscv_cpu_update_misa_c(cpu);\n> + riscv_cpu_update_misa_x(cpu);\n>\n> riscv_cpu_validate_misa_priv(env, &local_err);\n> if (local_err != NULL) {\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ryVtc/FY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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