[{"id":3680129,"web_url":"http://patchwork.ozlabs.org/comment/3680129/","msgid":"<CAKmqyKMq5+LaPe0bThEwCc87y=TAqLVzta5Cvxe887z1v+fR-g@mail.gmail.com>","list_archive_url":null,"date":"2026-04-21T23:23:41","subject":"Re: [PATCH v2 1/2] target/riscv: Add the implied rule for G extension","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 5:43 PM <frank.chang@sifive.com> wrote:\n>\n> From: Jim Shu <jim.shu@sifive.com>\n>\n> Add the missing implied rule from G to imafd_zicsr_zifencei.\n\n\n> riscv_cpu_validate_g() is also removed as imafd_zicsr_zifencei\n> can be enabled by the implied rule.\n\nBut what if a user enables G and disables one of these implied rules?\n\nAlistair\n\n>\n> Signed-off-by: Jim Shu <jim.shu@sifive.com>\n> Reviewed-by: Frank Chang <frank.chang@sifive.com>\n> ---\n>  target/riscv/cpu.c         | 14 +++++++++++-\n>  target/riscv/tcg/tcg-cpu.c | 44 --------------------------------------\n>  2 files changed, 13 insertions(+), 45 deletions(-)\n>\n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index 72c6f4f0f14..7978b4fad43 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -2247,6 +2247,18 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {\n>      },\n>  };\n>\n> +static RISCVCPUImpliedExtsRule RVG_IMPLIED = {\n> +    .is_misa = true,\n> +    .ext = RVG,\n> +    .implied_misa_exts = RVI | RVM | RVA | RVF | RVD,\n> +    .implied_multi_exts = {\n> +        CPU_CFG_OFFSET(ext_zicsr),\n> +        CPU_CFG_OFFSET(ext_zifencei),\n> +\n> +        RISCV_IMPLIED_EXTS_RULE_END\n> +    },\n> +};\n> +\n>  static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {\n>      .ext = CPU_CFG_OFFSET(ext_zcb),\n>      .implied_multi_exts = {\n> @@ -2634,7 +2646,7 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {\n>\n>  RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {\n>      &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,\n> -    &RVM_IMPLIED, &RVV_IMPLIED, NULL\n> +    &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL\n>  };\n>\n>  RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\n> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\n> index f3f78088956..840ef82350d 100644\n> --- a/target/riscv/tcg/tcg-cpu.c\n> +++ b/target/riscv/tcg/tcg-cpu.c\n> @@ -532,46 +532,6 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)\n>      cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11;\n>  }\n>\n> -static void riscv_cpu_validate_g(RISCVCPU *cpu)\n> -{\n> -    const char *warn_msg = \"RVG mandates disabled extension %s\";\n> -    uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD};\n> -    bool send_warn = cpu_misa_ext_is_user_set(RVG);\n> -\n> -    for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) {\n> -        uint32_t bit = g_misa_bits[i];\n> -\n> -        if (riscv_has_ext(&cpu->env, bit)) {\n> -            continue;\n> -        }\n> -\n> -        if (!cpu_misa_ext_is_user_set(bit)) {\n> -            riscv_cpu_write_misa_bit(cpu, bit, true);\n> -            continue;\n> -        }\n> -\n> -        if (send_warn) {\n> -            warn_report(warn_msg, riscv_get_misa_ext_name(bit));\n> -        }\n> -    }\n> -\n> -    if (!cpu->cfg.ext_zicsr) {\n> -        if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) {\n> -            cpu->cfg.ext_zicsr = true;\n> -        } else if (send_warn) {\n> -            warn_report(warn_msg, \"zicsr\");\n> -        }\n> -    }\n> -\n> -    if (!cpu->cfg.ext_zifencei) {\n> -        if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) {\n> -            cpu->cfg.ext_zifencei = true;\n> -        } else if (send_warn) {\n> -            warn_report(warn_msg, \"zifencei\");\n> -        }\n> -    }\n> -}\n> -\n>  static void riscv_cpu_validate_b(RISCVCPU *cpu)\n>  {\n>      const char *warn_msg = \"RVB mandates disabled extension %s\";\n> @@ -611,10 +571,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n>      CPURISCVState *env = &cpu->env;\n>      Error *local_err = NULL;\n>\n> -    if (riscv_has_ext(env, RVG)) {\n> -        riscv_cpu_validate_g(cpu);\n> -    }\n> -\n>      if (riscv_has_ext(env, RVB)) {\n>          riscv_cpu_validate_b(cpu);\n>      }\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=IOTCqvK7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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